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| s3c84bb/f84bb 8-bit cmos microcontrollers user's manual revision 1
important notice information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein. samsung reserves the right to make changes in its products or product specificat ions with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes. this publication does not c onvey to a purchaser of semiconductor devices described herein any license under the patent rights of samsung or others. samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does samsung assume any liability arising out of the application or use of any product or circuit and s pecifically disclaims any and all liability, including without limitation any consequential or incidental damages. "typical" parameters can and do vary in different applications. all operating parameters, including "typicals" must be validated for each customer application by the customer's technical experts. samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the samsung product could create a situation where personal injury or death may occur. should the buyer purchase or use a samsung product for any such unintended or unauthorized application, the buyer shall indemnify and hold samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of per sonal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that samsung was negligent regarding the design or manufacture of said product. s3c84bb/f84bb 8-bit cmos microcontrollers user's manual, revision 1 publication number: 20-s3-c84bb/f84bb-0800 ? 2000 samsung electronics all rights reserved. no part of this publication may be r eproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, record ing, or otherwise, without the prior written consent of samsung electronics. samsung electronics' microcontroller business has been awarded full iso-14001 certification (bsi certificate no. fm24653). all semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives. samsung electronics co., ltd. san #24 nongseo-ri, kiheung- eup yongin-city, kyunggi-do, korea c.p.o. box #37, suwon 449-900 tel: (82)-(31)-209-1907 fax: (82)-(31)-209-1899 home page: http://www.intl.samsungsemi.com printed in the republic of korea s3c84bb/f84bb microcontroller iii preface the s3c84bb/f84bb microcontroller user's manual is designed for application designers and programmers who are using the s3c84bb/84bb microcontroller for application development. it is organized in two main parts: part i programming model part ii hardware descriptions part i contains software-related information to familiari ze you with the microcontroller's architecture, programming model, instruction set, and interrupt structure. it has six chapters: chapter 1 product overview chapter 2 address spaces chapter 3 addressing modes chapter 4 control registers chapter 5 interrupt structure chapter 6 instruction set chapter 1, "product overview," is a high-level introduction to s3c84bb/f84bb with general product descriptions, as well as detailed information about individual pin characteristics and pin circuit types. chapter 2, "address spaces," describes program and data me mory spaces, the internal register file, and register addressing. chapter 2 also describes working register addressing, as well as system stack and user-defined stack operations. chapter 3, "addressing modes," contains detailed descrip tions of the addressing modes that are supported by the s3c8-series cpu. chapter 4, "control registers," contai ns overview tables for all mapped sy stem and peripheral control register values, as well as detailed one-page descriptions in a standardized format. you can use these easy-to-read, alphabetically organized, register descriptions as a quick-reference source when writing programs. chapter 5, "interrupt structure," de scribes the s3c84bb/f84bb interrupt st ructure in detail and further prepares you for additional information presented in the i ndividual hardware module descriptions in part ii. chapter 6, "instruction set," describes the features and conventions of the in struction set used for all s3c8-series microcontrollers. several summary tables are presented fo r orientation and reference. detailed descriptions of each instruction are presented in a standard format. each instruction description includes one or more practical examples of how to use the instruct ion when writing an application program. a basic familiarity with the information in part i w ill help you to understand the hardware module descriptions in part ii. if you are not yet familiar with the s3c-series microcontroller family and are reading this manual for the first time, we recommend that you first read chapters 1?3 carefully. then, briefly look over the detailed information in chapters 4, 5, and 6. later, you can reference the information in part i as necessary. part ii "hardware descriptions," has detailed info rmation about specific hardware components of the s3c84bb/f84bb microcontroller. also included in part ii are electrical, mechanical, flash mcu, and development tools data. it has 15 chapters: chapter 7 clock circuit chapter 8 reset and power-down chapter 9 i/o ports chapter 10 basic timer chapter 11 8-bit timer a/b/c(0/1) chapter 12 16-bit timer 1(0/1) chapter 13 serial i/o port chapter 14 uart(0/1) chapter 15 10-bit a/d converter chapter 16 8-bit d/a converter chapter 17 pattern generation module chapter 18 embedded flash memory interface chapter 19 electrical data chapter 20 mechanical data chapter 21 development tools two order forms are included at the back of this manual to facilitate customer order for s3c84bb/f84bb microcontrollers: the mask rom order form, and the ma sk option selection form. you can photocopy these forms, fill them out, and then forward them to your local samsung sales representative. s3c84bb/f84bb microcontroller v table of contents part i ? programming model chapter 1 product overview s3c8-series mi crocontro llers ................................................................................................... ....................1-1 s3c84bb/f84bb mi crocontroller.................................................................................................. ................1-1 featur es ....................................................................................................................... .................................1-2 block di agram .................................................................................................................. .............................1-3 pin assi gnment ................................................................................................................. ............................1-4 pin descr iptions ............................................................................................................... .............................1-6 pin circ uits ................................................................................................................... .................................1-9 chapter 2 address spaces overview....................................................................................................................... .................................2-1 program memo ry (r om)........................................................................................................... ....................2-2 register ar chitec ture.......................................................................................................... ...........................2-3 register page pointer (pp) ..................................................................................................... .............2-5 register set 1 ................................................................................................................. ......................2-6 register set 2 ................................................................................................................. ......................2-6 prime regist er s pace........................................................................................................... ................2-7 working r egisters .............................................................................................................. ..................2-8 using the regist er poin ters.................................................................................................... .............2-9 register a ddressi ng ............................................................................................................ ..........................2-11 common working register area (c0h?c fh) .....................................................................................2-13 4-bit working regi ster addr essing .............................................................................................. ........2-14 8-bit working regi ster addr essing .............................................................................................. ........2-16 system and us er stack .......................................................................................................... ......................2-18 chapter 3 addressing modes overview....................................................................................................................... .................................3-1 register addre ssing mode (r)................................................................................................... ...................3-2 indirect register addressing mode (i r) ......................................................................................... ...............3-3 indexed addressi ng mode (x).................................................................................................... ...................3-7 direct addre ss mode (da) ....................................................................................................... .....................3-10 indirect addr ess mode (ia) ..................................................................................................... ......................3-12 relative addr ess mode (ra)..................................................................................................... ....................3-13 immediate mode (i m) ............................................................................................................ ........................3-14 vi s3c84bb/f84bb microcontroller table of contents (continued) chapter 4 control registers overview ....................................................................................................................... ....................... 4-1 chapter 5 interrupt structure overview ....................................................................................................................... ................................ 5-1 interrupt types ................................................................................................................ ..................... 5-2 s3c84bb/f84bb inte rrupt stru cture .............................................................................................. ..... 5-3 interrupt vector addresses ..................................................................................................... ............. 5-5 enable/disable interrupt instructions (ei, di) ................................................................................. ..... 5-7 system-level interrupt control r egisters....................................................................................... ..... 5-7 interrupt processi ng control points ............................................................................................ ......... 5-8 peripheral interrupt control r egisters ......................................................................................... ........ 5-9 system mode regi ster ( sym) ..................................................................................................... ........ 5-10 interrupt mask r egister (imr) .................................................................................................. ........... 5-11 interrupt priority register (ipr).............................................................................................. .............. 5-12 interrupt request r egister (irq)............................................................................................... .......... 5-14 interrupt pending function types............................................................................................... ......... 5-15 interrupt source polling sequence .............................................................................................. ........ 5-16 interrupt serv ice rout ines ..................................................................................................... .............. 5-16 generating interrupt vector a ddresse s .......................................................................................... ..... 5-17 nesting of vect ored inte rrupts ................................................................................................. ............ 5-17 chapter 6 instruction set overview ....................................................................................................................... ................................ 6-1 data types..................................................................................................................... ...................... 6-1 register a ddressi ng............................................................................................................ ................. 6-1 addressi ng m odes ............................................................................................................... ................ 6-1 flags register (flags)......................................................................................................... .............. 6-6 flag descr iptions .............................................................................................................. ................... 6-7 instruction se t nota tion....................................................................................................... ................. 6-8 condition codes ................................................................................................................ .................. 6-12 instruction descrip tions....................................................................................................... ................. 6-13 s3c84bb/f84bb microcontroller vii table of contents (continued) part ii hardware descriptions chapter 7 clock circuit overview....................................................................................................................... .................................7-1 system clo ck circ uit ........................................................................................................... .................7-1 clock status duri ng power-dow n modes ........................................................................................... .7-2 system clock control register (clkco n) ......................................................................................... .7-3 chapter 8 reset and power-down system reset ................................................................................................................... .............................8-1 overview ....................................................................................................................... ........................8-1 normal mode rese t operation.................................................................................................... .........8-1 hardware re set values.......................................................................................................... ..............8-2 power-dow n m odes ............................................................................................................... .......................8-5 stop m ode ...................................................................................................................... ......................8-5 idle mode ...................................................................................................................... ........................8-6 chapter 9 i/o ports overview....................................................................................................................... .................................9-1 port data regist ers ............................................................................................................ ..................9-2 port 0 ......................................................................................................................... ...........................9-3 port 1 ......................................................................................................................... ...........................9-5 port 2 ......................................................................................................................... ...........................9-7 port 3 ......................................................................................................................... ...........................9-10 port 4 ......................................................................................................................... ...........................9-13 port 5 ......................................................................................................................... ...........................9-17 port 6 ......................................................................................................................... ...........................9-20 port 7 ......................................................................................................................... ...........................9-21 port 8 ......................................................................................................................... ...........................9-23 chapter 10 basic timer overview....................................................................................................................... .................................10-1 basic time r (b t)............................................................................................................... ....................10-1 basic timer control register (btcon) ........................................................................................... ....10-1 basic timer func tion descr iption............................................................................................... ..........10-3 viii s3c84bb/f84bb microcontroller table of contents (continued) chapter 11 8-bit timer a/b/c(0/1) 8-bit ti mer a .................................................................................................................. ............................... 11-1 overview ....................................................................................................................... ....................... 11-1 function de scription ........................................................................................................... ................. 11-2 timer a control r egister (t acon) ............................................................................................... ...... 11-3 block di agram.................................................................................................................. .................... 11-4 8-bit ti mer b .................................................................................................................. ............................... 11-5 overview ....................................................................................................................... ....................... 11-5 block di agram.................................................................................................................. .................... 11-5 timer b control r egister (t bcon) ............................................................................................... ...... 11-6 timer b pulse widt h calcul ations ............................................................................................... ........ 11-7 8-bit timer c (0/1 ) ............................................................................................................ ............................ 11-11 overview ....................................................................................................................... ....................... 11-11 timer c(0/1) control regist er (tccon0, t ccon1) .......................................................................... 11- 12 block di agram.................................................................................................................. .................... 11-13 chapter 12 16-bit timer 1(0/1) overview ....................................................................................................................... ................................ 12-1 function de scription ........................................................................................................... ................. 12-2 timer 1(0/1) control regist er (t1con0, t1con1) ............................................................................ 12-3 block di agram.................................................................................................................. .................... 12-6 chapter 13 serial i/o port overview ....................................................................................................................... ................................ 13-1 programming procedur e.......................................................................................................... ............ 13-1 sio control regi ster (s iocon) .................................................................................................. ........ 13-2 sio prescaler r egister (siops)................................................................................................. ......... 13-3 block di agram.................................................................................................................. .................... 13-3 serial i/o ti ming diagr ams..................................................................................................... ............. 13-4 s3c84bb/f84bb microcontroller ix table of contents (continued) chapter 14 uart(0/1) overview....................................................................................................................... .................................14-1 programming procedur e .......................................................................................................... ............14-1 uart control register (u artcon0, uart con1) ..............................................................................14-2 uart interrupt pending register (uartp nd)...................................................................................... .14-3 uart data register (udata0, udata1)............................................................................................ ..14-4 uart baud rate data regist er (brdata0, brdata1) .......................................................................14-4 baud rate ca lculat ions ......................................................................................................... ...............14-4 block di agram .................................................................................................................. .............................14-6 uart mode 0 func tion descr iption ............................................................................................... .........14-7 uart mode 1 func tion descr iption ............................................................................................... .........14-8 uart mode 2 func tion descr iption ............................................................................................... .........14-9 uart mode 3 func tion descr iption ............................................................................................... .........14-10 serial communication for multip rocessor confi gurations ....................................................................14-11 chapter 15 10-bit a/d converter overview....................................................................................................................... .................................15-1 function de scription........................................................................................................... ...........................15-1 conversion timing.............................................................................................................. ..................15-2 a/d converter control register (adaco n)........................................................................................ .15-2 internal referenc e voltage levels .............................................................................................. .........15-4 conversion timing.............................................................................................................. ..................15-4 internal a/d conv ersion pr ocedure.............................................................................................. ........15-5 chapter 16 10-bit d/a converter overview....................................................................................................................... .................................16-1 d/a conversion control register (a dacon) ......................................................................................1 6-2 d/a conversion data register (dadata) .......................................................................................... .16-2 block di agram .................................................................................................................. ....................16-3 chapter 17 pattern generation module overview....................................................................................................................... .................................17-1 pattern gner ation flow......................................................................................................... ................17-1 x s3c84bb/f84bb microcontroller table of contents (continued) chapter 18 embedded flash memory interface overview ....................................................................................................................... ................................ 18-1 flash memory cont rol regi sters ................................................................................................. .............. 18-3 sector erase ................................................................................................................... .............................. 18-5 progra mming .................................................................................................................... ............................ 18-9 data prot ection ................................................................................................................ ............................. 18-12 chapter 19 electrical data overview ....................................................................................................................... ....................... 19-1 chapter 20 mechanical data overview ....................................................................................................................... ....................... 20-1 chapter 21 development tools overview ....................................................................................................................... ................................ 21-1 shine .......................................................................................................................... .......................... 21-1 sama assembler ................................................................................................................. ................ 21-1 sasm88 ......................................................................................................................... ...................... 21-1 hex2rom ........................................................................................................................ ................... 21-1 target boards .................................................................................................................. .................... 21-1 tb84bb target board............................................................................................................ .............. 21-3 idle led ....................................................................................................................... ...................... 21-5 stop led ....................................................................................................................... .................... 21-5 s3c84bb/f84bb microcontroller xi list of figures figure title page number number 1-1 s3c84bb/f84bb block diagr am ...............................................................................1-3 1-2 s3c84bb/f84bb pin a ssignment (80- qfp)..............................................................1-4 1-3 s3c84bb/f84bb pin a ssignment (80- tqfp) ...........................................................1-5 1-4 pin circuit type b ( resetb ) ......................................................................................1-9 1-5 pin circui t type c.......................................................................................................1- 9 1-6 pin circuit type d (p0, p1, p2 except p2.3, p3, p8 except p8.4, p8.5) ...................1-10 1-7 pin circuit type d-1 (p4, p8.4, p8,5) .........................................................................1-10 1-8 pin circuit ty pe d-2 (p2. 3).........................................................................................1-11 1-9 pin circuit type e (adc0-adc7 )...............................................................................1-11 1-10 pin circuit type f (p 6) ...............................................................................................1-12 1-11 pin circuit type g (p5.7-p5 .4) ...................................................................................1-12 2-1 program memory address s pace .............................................................................. 2-2 2-2 internal register file organiza tion............................................................................. 2-4 2-3 register page pointer ( pp) ........................................................................................2-5 2-4 set 1, set 2, pr ime area regi ster ..............................................................................2-7 2-5 8-byte working regist er areas (s lices) .....................................................................2-8 2-6 contiguous 16-byte work ing register block .............................................................2-9 2-7 non-contiguous 16-byte wo rking register block .....................................................2-10 2-8 16-bit regist er pair ....................................................................................................2-1 1 2-9 register file addressi ng ............................................................................................2-12 2-10 common working r egister ar ea................................................................................ 2-13 2-11 4-bit working regi ster addre ssing ............................................................................ 2-15 2-12 4-bit working register addressing ex ample .............................................................2-15 2-13 8-bit working regi ster addre ssing ............................................................................ 2-16 2-14 8-bit working register addressing ex ample .............................................................2-17 2-15 stack o perati ons ........................................................................................................2- 18 3-1 register a ddressing ...................................................................................................3-2 3-2 working register addressi ng.....................................................................................3-2 3-3 indirect register addre ssing to regist er file .............................................................3-3 3-4 indirect register addre ssing to program memory .....................................................3-4 3-5 indirect working register a ddressing to regi ster f ile ..............................................3-5 3-6 indirect working register addre ssing to program or data memo ry ..........................3-6 3-7 indexed addressing to register file .......................................................................... 3-7 3-8 indexed addressing to program or da ta memory with short offs et ..........................3-8 3-9 indexed addressing to progr am or data memory ......................................................3-9 3-10 direct addressing fo r load instruct ions ..................................................................... 3-10 3-11 direct addressing for ca ll and jump inst ructions ......................................................3-11 3-12 indirect addressi ng.....................................................................................................3- 12 3-13 relative a ddressing ....................................................................................................3-1 3 3-14 immediate a ddressing ................................................................................................3-14 xii s3c84bb/f84bb microcontroller list of figures (continued) figure title page number number 4-1 register descr iption form at ...................................................................................... 4-4 5-1 s3c8-series in terrupt ty pes ..................................................................................... 5-2 5-2 s3c84bb/f84bb inte rrupt struct ure ......................................................................... 5-4 5-3 rom vector a ddress ar ea ........................................................................................ 5-5 5-4 interrupt func tion diagr am ........................................................................................ 5-8 5-5 system mode regi ster (sym ) ................................................................................... 5-10 5-6 interrupt mask r egister (i mr) ................................................................................... 5-11 5-7 interrupt request priority groups .............................................................................. 5-12 5-8 interrupt priority register (i pr) ................................................................................. 5-13 5-9 interrupt request r egister (i rq)............................................................................... 5-14 6-1 system flags regi ster (fla gs) ............................................................................... 6-6 7-1 main oscillator circuit (cryst al or ceramic oscillato r) .............................................. 7-1 7-2 system clock ci rcuit diagr am ................................................................................... 7-2 7-3 system clock control register (c lkcon) ............................................................... 7-3 9-1 port 0 control r egister (p0c on) .............................................................................. 9-4 9-2 port 1 control r egister (p1c on) .............................................................................. 9-6 9-3 port 2 high-byte contro l register (p 2conh) ........................................................... 9-8 9-4 port 2 low-byte contro l register (p 2conl) ............................................................ 9-9 9-5 port 3 high-byte contro l register (p 3conh) ........................................................... 9-11 9-6 port 3 low-byte contro l register (p 3conl) ............................................................ 9-12 9-7 port 4 high-byte contro l register (p 4conh) ........................................................... 9-14 9-8 port 4 low-byte contro l register (p 4conl) ............................................................ 9-15 9-9 port 4 interrupt contro l register (p 4int) .................................................................. 9-16 9-10 port 4 interrupt pending register (p4i ntpnd) ......................................................... 9-16 9-11 port 5 high-byte contro l register (p 5conh) ........................................................... 9-18 9-12 port 5 low-byte contro l register (p 5conl) ............................................................ 9-19 9-13 port 7 control r egister (p7c on) .............................................................................. 9-22 9-14 port 8 high-byte contro l register (p 8conh) ........................................................... 9-24 9-15 port 8 low-byte contro l register (p 8conl) ............................................................ 9-25 9-16 port 8 interrupt pending register (p8i ntpnd) ......................................................... 9-26 s3c84bb/f84bb microcontroller xiii list of figures (continued) page title page number number 10-1 basic timer control register (b tcon) .....................................................................10-2 10-2 basic timer bl ock diagr am ........................................................................................10-4 11-1 timer a control r egister (tac on)............................................................................ 11-3 11-2 timer a functional block di agram............................................................................. 11-4 11-3 timer b functional block di agram............................................................................. 11-5 11-4 timer b control r egister (tbc on)............................................................................ 11-6 11-5 timer b data register s (tbdatah, tb datal) .......................................................11-6 11-6 timer b output flip-flop waveforms in r epeat mode ..............................................11-8 11-7 timer c(0/1) control regi ster (tccon0, tccon1) .................................................11-12 11-8 timer c(0/1) functi onal block di agram ..................................................................... 11-13 12-1 timer 1(0/1) control regi ster (t1con0, t1con1) ...................................................12-4 12-2 timer a and timer 1(0/1) p ending register (tintpnd) ...........................................12-5 12-3 timer 1(0/1) functi onal block di agram...................................................................... 12-6 13-1 sio module control r egister (sio con).................................................................... 13-2 13-2 sio prescaler r egister (s iops) ................................................................................13-3 13-3 sio functional block diagr am ................................................................................... 13-3 13-4 sio timing in transmit/receive mode (tx at falling edge, siocon.4=0 ) ................13-4 13-5 sio timing in transmit/receive mode (tx at rising edge, siocon.4=1 ).................13-4 13-6 sio timing in receive-only mode (rising edge start) ..............................................13-5 14-1 uart control register (uartcon0, ua rtcon1) .................................................14-2 14-2 uart interrupt pending register (u artpnd) ..........................................................14-3 14-3 uart data register (udata0, udata1) .................................................................14-4 14-4 uart baud rate data regi ster (brdata0, brdata1) ..........................................14-4 14-5 uart functional block diagr am................................................................................ 14-6 14-6 timing diagram for uart mode 0 oper ation ............................................................14-7 14-7 timing diagram for uart mode 1 oper ation ............................................................14-8 14-8 timing diagram for uart mode 2 oper ation ............................................................14-9 14-9 timing diagram for uart mode 3 oper ation ............................................................14-10 14-10 connection example for multiprocesso r serial data co mmunicati ons ..................... 14-12 15-1 a/d converter control register (a dacon) ...............................................................15-2 15-2 a/d converter data regist er (addatah, addatal) ..............................................15-3 15-3 a/d converter ci rcuit diagr am................................................................................... 15-3 15-4 a/d converter timing diagr am .................................................................................. 15-4 15-5 recommended a/d converter circui t highest absolute accura cy............................ 15-5 16-1 d/a converter control register (a dacon) ...............................................................16-2 16-2 d/a converter data register (d adata) ....................................................................16-2 16-3 d/a converter ci rcuit diagr am................................................................................... 16-3 xiv s3c84bb/f84bb microcontroller list of figures (concluded) page title page number number 17-1 pattern gener ation fl ow ............................................................................................ 17-1 17-2 pg control regi ster (pgc on) .................................................................................. 17-2 17-3 pattern generation circuit di agram........................................................................... 17-2 18-1 flash memory control register (f mcon) ................................................................ 18-3 18-2 flash memory user programmi ng enable register (fmusr ).................................. 18-3 18-3 sectors in user program mode ................................................................................. 18-5 18-4 sectors erase wave fo rm......................................................................................... 18-6 18-5 program wa ve form .................................................................................................. 18-9 19-1 input timing for external interrupts (ports 4, port 8. 5, port 8.6) ............................... 19-5 19-2 input timing for reset .............................................................................................. 19-5 19-3 stop mode release timing initiated by reset ......................................................... 19-6 19-4 stop mode release timing in itiated by in terrupts ..................................................... 19-7 19-5 clock timing measurement at x in ............................................................................ 19-11 19-6 operating vo ltage range .......................................................................................... 19-11 20-1 s3c84bb/f84bb 80-qfp standard pack age dimensions(in millimeter s) ............... 20-1 20-2 s3c84bb/f84bb 80-tqfp standard pa ckage dimensions(in millimeter s)............. 20-2 21-1 smds product confi guration (smd s2+)................................................................... 21-2 21-2 tb84bb target boar d configurat ion ......................................................................... 21-3 21-3 40-pin connectors for tb84bb (s3c84bb, 80-qf p package) ................................ 21-6 21-4 tb84bb cable for 80-qfp adapt er........................................................................... 21-6 s3c84bb/f84bb microcontroller xv list of tables table title page number number 1-1 s3c84bb/f84bb pin de scriptions ( 80-qfp) ............................................................1-6 2-1 s3c84bb/f84bb regi ster type su mmary................................................................ 2-3 4-1 set 1 regist ers ........................................................................................................... 4-1 4-2 set 1, bank 0 register s..............................................................................................4-2 4-3 set 1, bank 1 register s..............................................................................................4-3 5-1 interrupt vectors .........................................................................................................5 -6 5-2 interrupt control r egister over view ........................................................................... 5-7 5-3 interrupt source contro l and data regi sters .............................................................5-9 6-1 instruction group summa ry........................................................................................6-2 6-2 flag notation conventi ons .........................................................................................6-8 6-3 instruction se t symbols..............................................................................................6-8 6-4 instruction nota tion convent ions ............................................................................... 6-9 6-5 opcode quick referenc e ...........................................................................................6-10 6-6 condition codes .........................................................................................................6-1 2 8-1 s3f84bb set 1 register values after reset ............................................................8-2 8-2 s3f84bb set 1, bank 0 register values after reset ...............................................8-3 8-3 s3f84bb set 1, bank 1 register values after reset ...............................................8-4 9-1 s3c84bb/f84bb port c onfiguration ov erview .........................................................9-1 9-2 port data regi ster summa ry......................................................................................9-2 14-1 commonly used baud rates generat ed by brdata0, brdata1 ..........................14-5 16-1 dadata setting to g enerate analog voltage ...........................................................16-3 xvi s3c84bb/f84bb microcontroller list of tables (continued) table title page number number 18-1 command in user program m ode ............................................................................. 18-2 19-1 absolute maxi mum rati ngs ....................................................................................... 19-2 19-2 d.c. electrical characterist ics ................................................................................... 19-2 19-3 a.c. electrical characterist ics ................................................................................... 19-5 19-4 input/output capacitanc e .......................................................................................... 19-6 19-5 data retention supply voltage in st op mode ........................................................... 19-6 19-6 a/d converter electric al characteri stics ................................................................... 19-8 19-7 d/a converter electric al characteri stics ................................................................... 19-8 19-8 flash memory d.c. electr ical characte ristics ........................................................... 19-9 19-9 flash memory a.c. electr ical characte ristics ........................................................... 19-9 19-10 main oscillator frequency (f osc1 )............................................................................. 19-10 19-11 main oscillator clock stabilization time (t st1 ).......................................................... 19-10 21-1 power selection se ttings for tb 84bb ....................................................................... 21-4 21-2 using single header pins as the input path for external tr igger sour ces ............... 21-5 s3c84bb/f84bb microcontroller xvii list of programming tips description page number chapter 2: address spaces using the page pointer for ram clear (page 0, p age 1).......................................................................... ....2-5 setting the regist er poin ters .................................................................................................. ......................2-9 using the rps to calculate the su m of a series of regi sters .................................................................... ..2-10 addressing the common wo rking regist er area .................................................................................... .....2-14 standard stack operations using push and pop ................................................................................... ...2-19 chapter 11: 8-bit timer a/b/c(0/1) to generate 38 khz, 1/3d uty signal th rough p2 .4 ................................................................................ .....11-9 to generate a one puls e signal th rough p2.4 .................................................................................... .......11-10 using the timer a.............................................................................................................. ............................11-14 using the timer b.............................................................................................................. ............................11-15 using the ti mer c( 0/1) ......................................................................................................... .........................11-16 chapter 12: 16-bit timer 1(0/1) using the ti mer 1( 0)........................................................................................................... ...........................12-7 chapter 13: serial i/o port use internal clock to trans mit and receive serial data......................................................................... .....13-5 chapter 15: 10-bit a/d converter configuring a/ d conver ter ...................................................................................................... ......................15-6 chapter 17: pattern generation module using the pattern generation................................................................................................... .....................17-3 chapter 18: embedded flash memory interface sector erase................................................................................................................... ...............................18-7 progra mming .................................................................................................................... .............................18-10 option sector programming(hard lock pr otection in user program m ode)................................................ 18-13 s3c84bb/f84bb microcontroller xix list of register descriptions register full register name page identifier number adacon a/d, d/a converte r control r egister ......................................................................... 4-5 brdata0 uart0 baud rate data regi ster .............................................................................. 4-6 brdata1 uart1 baud rate data regi ster .............................................................................. 4-7 btcon basic timer c ontrol regi ster ..................................................................................... 4-8 clkcon system clock control regi ster .................................................................................. 4-9 flags system flags regist er ............................................................................................... 4-10 fmcon flash memory c ontrol regi ster ................................................................................. 4-11 imr interrupt ma sk regist er .............................................................................................. 4-12 iph instruction pointe r (high by te) .................................................................................. 4-13 ipl instruction pointe r (low by te) ................................................................................... 4-13 ipr interrupt priori ty regist er ........................................................................................... 4-14 irq interrupt reques t regist er ......................................................................................... 4-15 p0con port 0 cont rol regist er............................................................................................... 4-1 6 p1con port 1 cont rol regist er............................................................................................... 4-1 7 p2conh port 2 control regi ster (high byte)............................................................................ 4-18 p2conl port 2 control r egister (low byte) ............................................................................ 4-19 p3conh port 3 control regi ster (high byte)............................................................................ 4-20 p3conl port 3 control r egister (low byte) ............................................................................ 4-21 p4conh port 4 control regi ster (high byte)............................................................................ 4-22 p4conl port 4 control r egister (low byte) ............................................................................ 4-23 p4int port 4 interrupt control regi ster ................................................................................ 4-24 p4intpnd port 4 interrupt pending regi ster............................................................................... 4-25 p5conh port 5 control regi ster (high byte)............................................................................ 4-26 p5conl port 5 control r egister (low byte) ............................................................................ 4-27 p7con port 7 cont rol regist er............................................................................................... 4-2 8 p8conh port 8 control regi ster (high byte)............................................................................ 4-29 p8conl port 8 control r egister (low byte) ............................................................................ 4-30 p8intpnd port 8 interrupt pending regi ster............................................................................... 4-31 pgcon pattern generation control regi ster.......................................................................... 4-32 xx s3c84bb/f84bb microcontroller list of register descriptions (continued) register full register name page identifier number pp register page pointer ................................................................................................4-33 rp0 register pointer 0 .......................................................................................................4- 34 rp1 register pointer 1 .......................................................................................................4- 34 siocon sio cont rol regi ster ..................................................................................................4- 35 siops sio prescale r regist er...............................................................................................4-36 sph stack pointer (high byte ) ...........................................................................................4-37 spl stack pointer (low byte ) ............................................................................................4-37 sym system mode register ...............................................................................................4-38 t1con0 timer 1(0) c ontrol regi ster ........................................................................................4-39 t1con1 timer 1(1) c ontrol regi ster ........................................................................................4-40 tacon timer a cont rol regist er ............................................................................................4-41 tbcon timer b cont rol regist er ............................................................................................4-42 tccon0 timer c(0) c ontrol regi ster .......................................................................................4-43 tccon1 timer c(1) c ontrol regi ster .......................................................................................4-44 tintpnd timer a,1 interr upt pending r egister .........................................................................4-45 uartcon0 uart0 cont rol regist er.............................................................................................4-4 6 uartcon1 uart1 cont rol regist er.............................................................................................4-4 7 uartpnd uart1(0) p ending regist er ...................................................................................... 4-48 s3c84bb/f84bb microcontroller xxi list of instruction descriptions instruction full register name page mnemonic number adc add with carry ............................................................................................................ 6 -14 add add ....................................................................................................................... ...... 6-15 and logica l and ............................................................................................................... 6-16 band bi t and.................................................................................................................. ..... 6-17 bcp bit compar e ............................................................................................................... 6-18 bitc bit co mplem ent.......................................................................................................... 6 -19 bitr bit reset ................................................................................................................. .... 6-20 bits bit set .................................................................................................................. ....... 6-21 bor bi t or .................................................................................................................... ..... 6-22 btjrf bit test, jump relative on false ............................................................................... 6-23 btjrt bit test, jump relative on true................................................................................. 6-24 bxor bit xor.................................................................................................................. ..... 6-25 call call procedur e........................................................................................................... . 6-26 ccf complement carry fl ag ............................................................................................. 6-27 clr clear ..................................................................................................................... ...... 6-28 com comp lement ............................................................................................................... 6 -29 cp co mpare.................................................................................................................... . 6-30 cpije compare, incremen t, and jump on equal ................................................................. 6-31 cpijne compare, incremen t, and jump on n on-equal ......................................................... 6-32 da decima l adju st ........................................................................................................... 6- 33 dec de crement................................................................................................................. . 6-35 decw decrem ent word ........................................................................................................ 6-3 6 di disable in terrupts ....................................................................................................... 6-3 7 div divide (unsi gned)....................................................................................................... 6- 38 djnz decrement and ju mp if non- zero.............................................................................. 6-39 ei enable in terrupt s ........................................................................................................ 6- 40 enter enter ................................................................................................................... ........ 6-41 exit exit..................................................................................................................... ......... 6-42 idle idle operat ion........................................................................................................... .. 6-43 inc incr ement .................................................................................................................. . 6-44 incw increm ent wo rd.......................................................................................................... 6 -45 iret interr upt re turn .......................................................................................................... 6-46 jp jump....................................................................................................................... .... 6-47 jr jump relative............................................................................................................. 6 -48 ld load....................................................................................................................... ..... 6-49 ldb load bit .................................................................................................................. .... 6-51 xxii s3c84bb/f84bb microcontroller list of instruction descriptions (continued) instruction full register name page mnemonic number ldc/lde load memo ry........................................................................................................... ...6-52 ldcd/lded load memory and decrem ent .................................................................................... 6-54 ldci/ldei load memory and increm ent...................................................................................... 6-55 ldcpd/ldepd load memory wi th pre-decr ement............................................................................. 6-56 ldcpi/ldepi load memory wi th pre-incr ement .............................................................................. 6-57 ldw load word .................................................................................................................. 6-58 mult multiply (unsi gned) .....................................................................................................6 -59 next next..................................................................................................................... ........6-60 nop no o peratio n .............................................................................................................. 6-61 or logi cal or ................................................................................................................. .6-62 pop pop from stack ...........................................................................................................6 -63 popud pop user sta ck (decrement ing)................................................................................. 6-64 popui pop user sta ck (increment ing) .................................................................................. 6-65 push push to stack............................................................................................................ ..6-66 pushud push user sta ck (decrement ing) ............................................................................... 6-67 pushui push user st ack (increm enting) ................................................................................6-68 rcf reset ca rry fl ag.........................................................................................................6 -69 ret re turn .................................................................................................................... .....6-70 rl rota te left ................................................................................................................ ..6-71 rlc rotate left through ca rry ........................................................................................... 6-72 rr rotate right............................................................................................................... .6-73 rrc rotate right through ca rry......................................................................................... 6-74 sb0 select bank 0............................................................................................................. .6-75 sb1 select bank 1............................................................................................................. .6-76 sbc subtract with ca rry ..................................................................................................... 6- 77 scf set ca rry fl ag............................................................................................................ .6-78 sra shift right arithmetic ..................................................................................................6-7 9 srp/srp0/srp1 set register pointer............................................................................................ ........6-80 stop stop operat ion........................................................................................................... .6-81 sub s ubtract .................................................................................................................. ....6-82 swap swap nibbl es............................................................................................................. .6-83 tcm test complem ent under ma sk ................................................................................... 6-84 tm test under mask .........................................................................................................6-8 5 wfi wait fo r inte rrupt ........................................................................................................ .6-86 xor logical excl usive or ..................................................................................................6-87 s3c84bb/f84bb pr oduct overview 1-1 1 product overview s3c8-series microcontrollers samsung's s3c8-series of 8-bit single-chip cmos microc ontrollers offers a fast and efficient cpu, a wide range of integrated peripherals, and various mask-programm able rom sizes. the major cpu features are: ? efficient register-oriented architecture ? selectable cpu clock sources ? idle and stop power-down mode released by interrupt or reset ? built-in basic timer with watchdog function a sophisticated interrupt structure recognizes up to eight interrupt levels. each level can have one or more interrupt sources and vectors. fast interrupt processing (within a minimum of four cpu clocks) can be assigned to specific interrupt levels. s3c84bb/f84bb microcontroller the s3c84bb/f84bb single-chip cmos microcontrolle rs are fabricated using the highly advanced cmos process, based on samsung?s latest cpu architecture. the s3c84bb is a microcontroller with a 64k-byte mask-programmable rom embedded. the s3f84bb is a microcontroller with a 64k-byte full-flash rom embedded. using a proven modular design approach, sa msung engineers have successfully developed the s3c84bb/f84bb by integrating the following per ipheral modules with the powerful sam8 core: ? nine programmable i/o ports, including eight 8-bit ports and one 6-bit ports, for a total of 70 pins. ? ten bit-programmable pins for external interrupts. ? one 8-bit basic timer for oscillation stab ilization and watchdog function (system reset). ? four 8-bit timer/counter and two 16-bit ti mer/counter with selectable operating modes. ? tow asynchronous uart ? one synchronous sio ? one 8-bit d/a converter ? 8-channel a/d converter the s3c84bb/f84bb is versatile microcontroller for cd-rom and adc application, et c. they are currently available in 80-pin qfp and 80-pin tqfp package. product overview s3c84bb/f84bb 1-2 features cpu ? sam88rc cpu core memory ? 2064-bytes internal register file ? 64k-bytes internal program memory - s3c84bb: mask rom - s3f84bb: flash type memory oscillation sources ? crystal, ceramic ? cpu clock divider (1/1, 1/2, 1/8, 1/16) instruction set ? 78 instructions ? idle and stop instructions added for power- down modes instruction execution time ? 400 ns at 10-mhz f osc (minimum) interrupts ? 24 interrupt sources with 24 vector. ? 8 level, 24 vector interrupt structure i/o ports ? total 70 bit-programmable pins timers and timer/counters ? one programmable 8-bit basic timer ( bt ) for oscillation stabilization control or watchdog-timer function. ? one 8-bit timer/counter ( timer a ) with three operating modes; interval mode, capture mode and pwm mode. ? one 8-bit timer/counter ( timer b ) carrier frequency (or pwm) generator. ? two 8-bit timer with pwm mode ( timer c0,c1 ) ? two 16-bit capture timer/counter ( timer 10,11 ) with two operating modes; interval mode, capture mode for pulse period or duty. a/d converter ? 10-bit resolution ? eight analog input channels ? 20us conversion speed at 10mhz f adc clock. d/a converter ? 8-bit d/a converter ? r/2r resistor method ? one d/a output (daout) asynchronous uart ? full duplex 2 channels uarts ? programmable baud rate ? supports serial dat a transmit/receive operations with 8-bit, 9-bit in uart synchronous sio ? programmable baud rate ? one synchronous serial i/o module pattern generation module ? pattern generation module triggered by timer match signal and s/w. operating temperature range ? -25 c to + 85 c operating voltage range ? 2.7 v to 5.5 v at 10mhz f osc package type ? 80 pin qfp, 80 pin tqfp s3c84bb/f84bb pr oduct overview 1-3 block diagram i/o port and interrupt control sam88rc cpu 64k-byte rom 2064-byte ram osc/resetb 8-bit basic timer 8-bit timer /countera,b 8-bit timer/ counterc0,c1 16-bit timer /counter10,11 port 0 port 1 a/d port 2 p2.0-p2.7 x in x out resetb p2.7/taout p2.6/tacap p2.5/tack p3.6/tcout1 p2.4/tbout p3.4/t1out0 p1.0-p1.7 p0.0-p0.7 av ref av ss port 3 p3.0-p3.7 port 4 p4.0-p4.7/ int0~int7 port 5 p5.0-p5.7 port 6 p6.0-p6.7 sio/ uart0,1 pg p3.7/tcout0 p0.0~p0.7/ pg0~pg7 p3.2/t1cap0 p3.0/t1ck0 p3.5/t1out1 p3.3/t1cap1 p3.1/t1ck1 p2.2/sck p2.1/si p2.0/so p5.3/rxd0 p5.2/txd0 p5.1/rxd1 p5.0/txd1 port 8 port 7 d/a p7.0-p7.7/ adc0~adc7 p8.0-p8.5/ int8,int9 p2.3/ daout figure 1-1. s3c84bb/f84bb block diagram product overview s3c84bb/f84bb 1-4 pin assignment p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 p0.7/pg7 p0.6/pg6 p0.5/pg5 p0.4/pg4 p0.3/pg3 p0.2/pg2 p0.1/pg1 p0.0/pg0 p2.7/taout p2.6/tacap p2.5/tack p2.4/tbpwm p2.3/daout p2.2/sck p2.1/si p2.0/so p5.7 p5.6/sdat p5.5/sclk vdd1 vss1 xout xin test p5.4 p5.3/rxd0 resetb p5.2/txd0 p5.1/rxd1 p5.0/txd1 p3.7/tcout1 p3.6/tcout0 s3c84bb/f84bb (80-qfp-1420c) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p3.5/t1out1 p3.4/t1out0 p3.3/t1cap1 p3.2/t1cap0 p3.1/t1ck1 p3.0/t1ck0 p4.7/int7 p4.6/int6 p4.5/int5 p4.4/int4 p4.3/int3 p4.2/int2 p4.1/int1 p4.0/int0 p7.7/adc7 p7.6/adc6 p8.0 p8.1 p8.2 p8.3 p8.4/int8 p8.5/int9 p6.0 p6.1 p6.2 p6.3 p6.4 vdd2 vss2 p6.5 p6.6 p6.7 p7.0/adc0 p7.1/adc1 p7.2/adc2 p7.3/adc3 avss avref p7.4/adc4 p7.5/adc5 figure 1-2. s3c84bb/f84bb pin assignment (80-qfp) s3c84bb/f84bb pr oduct overview 1-5 pin assignment s3c84bb/f84bb (80-tqfp-1212) p8.1 p8.0 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 p0.7/pg7 p0.6/pg6 p0.5/pg5 p0.4/pg4 p0.3/pg3 p0.2/pg2 p0.1/pg1 p0.0/pg0 p2.7/taout p2.6/tacap p2.5/tack p2.4/tbpwm p2.3/daout p2.2/sck p2.1/si p2.0/so p5.7 p5.6/sdat p5.5/sclk vdd1 vss1 xout xin test p5.4 p5.3/rxd0 resetb p5.2/txd0 p5.1/rxd1 p5.0/txd1 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p3.7/tcout1 p3.6/tcout0 p3.5/t1out1 p3.4/t1out0 p3.3/t1cap1 p3.2/t1cap0 p3.1/t1ck1 p3.0/t1ck0 p4.7/int7 p4.6/int6 p4.5/int5 p4.4/int4 p4.3/int3 p4.2/int2 p4.1/int1 p4.0/int0 p7.7/adc7 p7.6/adc6 p7.5/adc5 p7.4/adc4 p8.2 p8.3 p8.4/int8 p8.5/int9 p6.0 p6.1 p6.2 p6.3 p6.4 vdd2 vss2 p6.5 p6.6 p6.7 p7.0/adc0 p7.1/adc1 p7.2/adc2 p7.3/adc3 avss avref figure 1-3. s3c84bb/f84bb pin assignment (80-tqfp) product overview s3c84bb/f84bb 1-6 pin descriptions table 1-1. s3c84bb/f84bb pin descriptions (80-qfp) pin name pin type pin description circuit type pin number share pins p0.0 - p0.7 i/o bit programmable port; input or output mode selected by software; input or push-pull output. software assignable pull-up. alternately, p0.0-p0.7 can be used as the pg output port (pg0-pg7). d 80-73 pg0-pg7 p1.0 - p1.7 i/o bit programmable port; input or output mode selected by software; input or push-pull output. software assignable pull-up. d 72-65 p2.0 - p2.7 i/o bit programmable port; input or output mode selected by software; input or push-pull output. software assignable pull-up. alternately, p2.0~p2.7 can be used as i/o for timera, timerb, d/a, sio d,d-2 8-1 so si sck daout tbpwm tack tacap taout p3.0 - p3.7 i/o bit programmable port; input or output mode selected by software; input or push-pull output. software assignable pull-up. alternately, p3.0~p3.7 can be used as i/o for timerc0/c1, timer10/11 d 30?23 t1ck0 t1ck1 t1cap0 t1cap1 t1out0 t1out1 tcout0 tcout1 s3c84bb/f84bb pr oduct overview 1-7 table 1-1. s3c84bb/f84bb pin d escriptions (80-qfp) (continued) pin name pin type pin description circuit type pin number share pins p4.0 - p4.7 i/o bit programmable port; input or output mode selected by software; input or push-pull output. software assignable pull-up. p4.0-p4.7 can alternately be used as inputs for external interrupts int0-int7, respectively (with noise filters and interrupt controller) d-1 38-31 int0? int7 p5.0 - p5.7 i/o bit programmable port; input or output mode selected by software; input or push-pull output. software assignable pull-up. alternately, p5.0~p5.3 can be used as i/o for serial por, uart0, uart1, respectively. g 22-17,11-9 txd1 rxd1 txd0 rxd0 p6.0 - p6.7 o n-channel, open-drain output only port. f 58?54,51-49 p7.0 - p7.7 i general-purpose di gital input ports. alternatively used as analog input pins for a/d converter modules. e 48-45,42-39 adc0- adc7 p8.0 - p8.5 i/o bit programmable port; input or output mode selected by software; input or push-pull output. software assignable pull-up. p8.4, p8.5 can alternately be used as inputs for external interrupts int8, int9, respectively (with noise filters and interrupt controller) d,d-1 64-59 int8,int9 product overview s3c84bb/f84bb 1-8 table 1-1. s3c84bb/f84bb pin d escriptions (80-qfp) (continued) pin name pin type pin description circuit type pin number share pins ad0 - ad7 i analog input pins for a/d converter module. alternatively used as general-purpose digital input port 7. e 48?45 42?39 p7.0?p7.7 avref, avss - a/d converter reference voltage and ground - 43, 44 - rxd0, rxd1 i/o serial data rxd pin for receive input and transmit output (mode 0) d 18, 21 p5.3, p5.1 txd0, txd1 o serial data txd pin for transmit output and shift clock input (mode 0) d 20, 22 p5.2, p5.0 tack i external clock input pins for timer a d 3 p2.5 tacap i capture input pins for timer a d 2 p2.6 taout o pulse width modulation output pins for timer a d 1 p2.7 tbpwm o carrier frequency output pins for timer b d 4 p2.4 tcout0 tcout1 o timer c 8-bit pwm mode output or counter match toggle output pins d 24,23 p3.6,p3.7 t1ck0 t1ck1 i external clock input pins for timer 1 d 39,30 p3.0,p3.1 t1cap0 t1cap1 i capture input pins for timer 1 d 28,27 p3.2,p3.3 t1out0 t1out1 o timer 1 16-bit pwm mode output or counter match toggle output pins d 26,25 p3.4,p3.5 si,so,sck i/o synchronous sio pins d 7,8,9 p2.1,p2.0, p2.2 resetb i system reset pin (pull-up resistor: 240 k ? ) b 19 - test i pull ? down register connected internally - 16 - vdd1, vdd2, vss1, vss2 - power input pins - 12,53, 13,52 - xin, xout - main oscillator pins - 15,14 - s3c84bb/f84bb pr oduct overview 1-9 pin circuits schmitt trigger in v dd pull-up resistor figure 1-4. pin circuit type b ( resetb ) p-channel n-channel v dd out output disable data figure 1-5. pin circuit type c product overview s3c84bb/f84bb 1-10 i/o output disable data pin circuit type c pull-up enable v dd figure 1-6. pin circuit type d (p0, p1, p2 except p2.3, p3, p8 except p8.4, p8.5) i/o output disable data pin circuit type c pull-up enable v dd noise filter ext.int input normal v dd figure 1-7. pin circuit type d-1 (p4, p8.4, p8.5) s3c84bb/f84bb pr oduct overview 1-11 i/o output disable data pin circuit type c pull-up enable v dd to dac figure 1-8. pin circuit type d-2 (p2.3) in data adc in en to adc figure 1-9. pin circuit type e (adc0-adc7) product overview s3c84bb/f84bb 1-12 n-channel out data figure 1-10. pin circuit type f (p6) i/o pull-up enable v dd input normal p-channel n-channel v dd output disable data open-drain figure 1-11. pin circuit type g (p5.7-p5.4) s3c84bb/f84bb address spaces 2-1 2 address spaces overview the s3c84bb/f84bb microcontroller has two types of address space: ? internal program memory (rom) ? internal register file (ram) a 16-bit address bus supports program memory operations. a separate 8-bit register bus carries addresses and data between the cpu and the register file. the s3c84bb/f84bb has an internal 64-kbyte mask- programmable rom/flash rom and 2064-byte ram. address spaces s3c84bb/f84bb 2-2 program memory (rom) program memory (rom) stores program codes or table data. the s3c84 bb has 64-kbytes of internal mask programmable program memory. the program memory addr ess range is therefore 0h?ffffh (see figure 2-1). the first 256 bytes of the rom (0h-0ffh) are reserved for interrupt vector addresses. unused locations in this address range can be used as normal program memory. if y ou use the vector address area to store a program code, be careful not to overwrite the vect or addresses stored in these locations. the rom address at which a program exec ution starts after a reset is 0100h. (decimal) 65,535 255 (hex) ffffh 0ffh 0h 0 64-kbyte interrupt vector area figure 2-1. program memory address space s3c84bb/f84bb address spaces 2-3 register architecture in the s3c84bb/f84bb implementation, the upper 64-byte area of register files is expanded two 64-byte areas, called set 1 and set 2 . the upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank 1), and the lower 32-byte area is a single 32-byte common area. in addition, set 2 is logically expanded 8 separately addressable register pages, page 0?page 7. in case of s3c84bb/f84bb the total number of addressabl e 8-bit registers is 2,144. of these 2,144 registers, 16 bytes are for cpu and system control registers, 64 bytes are for peripheral control and data registers, 16 bytes are used as a shared working registers, and 2,048 registers are for general-purpose use. you can always address set 1 register locations, regardless of which of the 8 register pages is currently selected. set 1 locations, however, can only be addr essed using direct addressing modes. the extension of register space into separately addr essable areas (sets, banks, and pages) is supported by various addressing mode restrictions, the select bank instructions, sb0 and sb1, and the register page pointer (pp). specific register types and the area (in bytes) that they occupy in the regi ster file are summarized in table 2?1. table 2-1. s3c84bb/f84bb register type summary register type number of bytes general-purpose registers (including 16-byte common working register area, the 192- byte prime register area, and the 64-byte set 2 area) cpu and system control registers mapped clock, peripheral, i/o control, and data registers 2,064 16 64 total addressable bytes 2,144 address spaces s3c84bb/f84bb 2-4 bank 1 ffh e0h 32 bytes e0h dfh d0h cfh c0h set 2 general-purpose data registers (indirect register, indexed mode, and stack operations) c0h bfh 00h ffh 192 bytes 64 bytes 256 bytes system and peripheral control registers (register addressing mode) system and peripheral control registers (register addressing mode) general purpose register (register addressing mode) prime data registers (all addressing modes) set1 page 1 bank 0 page 0 page 0 page 2 page 3 page 4 page 5 page 6 page 7 figure 2-2. internal register file organization s3c84bb/f84bb address spaces 2-5 register page pointer (pp) the s3c8-series architecture supports the logical expansion of the physical 2,064-byte inte rnal register file (using an 8-bit data bus) into as many as 16 separately addre ssable register pages. page addressing is controlled by the register page pointer (pp, dfh). in the s3c84bb/f 84bb microcontroller, a paged register file expansion is implemented for data registers, and the register page pointer must be changed to address other pages. after a reset, the page pointer's source value (lower ni bble) and the destination value (upper nibble) are always "0000", automatically selecting page 0 as the sour ce and destination page for register addressing. register page pointer (pp) dfh ,set 1, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 destination register page selection bits: destination: page 0 source register page selection bits: source: page 0 note: in the s3c84bb/f84bb microcontroller, pages 0~7 are implemented. a hardware reset operation writes the 4-bit destination and source values show n above to the register page pointer. these values should be modified to address other pages. 0000 0000 destination: page 7 source: page 7 0111 0111 ... ... ... ... figure 2-3. register page pointer (pp) programming tip ? using the page pointer for ram clear (page 0, page 1) ld pp,#00h ; destination 0, source 0 srp #0c0h ld r0,#0ffh ; page 0 ram clear starts ramcl0 clr @r0 djnz r0,ramcl0 clr @r0 ; r0 = 00h ld pp,#10h ; destination 1, source 0 ld r0,#0ffh ; page 1 ram clear starts ramcl1 clr @r0 djnz r0,ramcl1 clr @r0 ; r0 = 00h note: you should refer to page 6-39 and use djnz instruction pr operly when djnz instruction is used in your program. address spaces s3c84bb/f84bb 2-6 register set 1 the term set 1 refers to the upper 64 bytes of the register file, locations c0h?ffh. the upper 32-byte area of this 64-byte space (e 0h?ffh) is expanded two 32-byte register banks, bank 0 and bank 1 . the set register bank instructions, sb0 or sb1, are used to address one bank or the other. a hardware reset operation always selects bank 0 addressing. the upper two 32-byte areas (bank 0 and bank 1) of set 1 (e0h?ffh) contains 64 mapped system and peripheral control registers. the lower 32-byte area contains 16 system regist ers (d0h?dfh) and a 16-byte common working register area (c0h?cfh). you can use the common working register area as a ?scratch? area for data operations being performed in ot her areas of the register file. registers in set 1 locations are directly accessible at all times using register addressing mode. the 16-byte working register area can only be accessed using work ing register addressing (for more information about working register addressing, please refe r to chapter 3, ?addressing modes.?) register set 2 the same 64-byte physical space that is used for set 1 locations c0h?ffh is logically duplicated to add another 64 bytes of register space. this expanded ar ea of the register file is called set 2 . for the s3c84bb/f84bb, the set 2 address range (c0h?ffh) is accessible on pages 0-7. the logical division of set 1 and set 2 is maintained by means of addressing mode restrictions. you can use only register addressing mode to access set 1 locations. in order to access registers in set 2, you must use register indirect addressing mode or indexed addressing mode. the set 2 register area is commonly used for stack operations. s3c84bb/f84bb address spaces 2-7 prime register space the lower 192 bytes (00h?bfh) of the s3c84bb/f84bb's eight 256-byte register pages is called prime register area. prime registers can be accessed using any of t he seven addressing modes (see chapter 3, "addressing modes.") the prime register area on page 0 is immediately addre ssable following a reset. in order to address prime registers on pages 0, or 1 you must set the register page pointer (pp) to the appropr iate source and destination values. page 7 ffh f0h e0h d0h c0h set 1 bank 0 peripheral and i/o general-purpose cpu and system control ffh ffh c0h set 2 00h prime space bfh bank 1 ... page 0 page 0 ffh figure 2-4. set 1, set 2, prime area register address spaces s3c84bb/f84bb 2-8 working registers instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. when 4-bit working register addressing is used, the 256-by te register file can be seen by the programmer as one that consists of 32 8-byte register groups or "slices." each slice comprises of eight 8-bit registers. using the two 8-bit register pointers, rp1 and rp0, two working register slic es can be selected at any one time to form a 16-byte working register block. using the regist er pointers, you can move this 16-byte register block anywhere in the addressable register file, except for the set 2 area. the terms slice and block are used in this manual to help y ou visualize the size and relative locations of selected working register spaces: ? one working register slice is 8 bytes (eight 8-bit worki ng registers, r0?r7 or r8?r15) ? one working register block is 16 bytes (sixteen 8-bit working registers, r0?r15) all the registers in an 8-byte working register slice hav e the same binary value for their five most significant address bits. this makes it possible for each register pointer to point to one of the 24 slices in the register file other than set 2. the base addresses for the two selected 8-byte regi ster slices are contained in register pointers rp0 and rp1. after a reset, rp0 and rp1 always point to t he 16-byte common area in set 1 (c0h?cfh). each register pointer points to one 8-byte slice of the register space, selecting a total 16- byte working register block. 1 1 1 1 1 x x x rp1 (registers r8-r15) rp0 (registers r0-r7) slice 32 slice 31 ~ ~ cfh c0h ffh f8h f7h f0h fh 8h 7h 0h slice 2 slice 1 10h set 1 only 0 0 0 0 0 x x x figure 2-5. 8-byte working register areas (slices) s3c84bb/f84bb address spaces 2-9 using the register pointers after a reset, rp# point to the working register common area: rp0 points to addresses c0h?c7h, and rp1 points to addresses c8h?cfh. to change a register pointer value, you load a new value to rp0 and/or rp1 using an srp or ld instruction. (see figures 2-6 and 2-7). with working register addressing, you can only access those tw o 8-bit slices of the regist er file that are currently pointed to by rp0 and rp1. you can not, however, use the register pointers to select a working register space in set 2, c0h?ffh, because these locations can be acce ssed only using the indirect register or indexed addressing modes. the selected 16-byte working register block usually c onsists of two contiguous 8- byte slices. as a general programming guideline, it is recommended that rp0 point to the "lower" slice and rp1 point to the "upper" slice (see figure 2-6). because a register pointer can point to either of the tw o 8-byte slices in the working register block, you can flexibly define the working register area to support program requirements. programming tip ? setting the register pointers srp #70h ; rp0 70h, rp1 78h srp1 #48h ; rp0 no change, rp1 48h, srp0 #0a0h ; rp0 a0h, rp1 no change clr rp0 ; rp0 00h, rp1 no change ld rp1,#0f8h ; rp0 no change, rp1 0f8h fh (r15) 0h (r0) 8-byte slice 16-byte contiguous working register block register file contains 32 8-byte slices rp0 rp1 8h 7h 0 0 0 0 1 x x x 0 0 0 0 0 x x x 8-byte slice figure 2-6. contiguous 16-byte working register block address spaces s3c84bb/f84bb 2-10 cfh (r15) 0h (r0) 8-byte slice 16-byte non-contiguou s working register block register file contains 32 8-byte slices rp0 rp1 7h (r7) 1 1 0 0 1 x x x 0 0 0 0 0 x x x 8-byte slice c8h (r8) figure 2-7. non-contiguous 16-byte working register block programming tip ? using the rps to calculate the sum of a series of registers calculate the sum of registers 80h?85h using the register pointer. the r egister addresses from 80h through 85h contain the values 10h, 11h, 12h , 13h, 14h, and 15h, respectively: srp0 #80h ; rp0 80h add r0,r1 ; r0 r0 + r1 adc r0,r2 ; r0 r0 + r2 + c adc r0,r3 ; r0 r0 + r3 + c adc r0,r4 ; r0 r0 + r4 + c adc r0,r5 ; r0 r0 + r5 + c the sum of these six registers, 6fh, is located in the register r0 (80h). the instruction string used in this example takes 12 bytes of instruction c ode and its execution time is 36 cycles. if the register pointer is not used to calculate the sum of these registers, the fo llowing instruction sequence would have to be used: add 80h,81h ; 80h (80h) + (81h) adc 80h,82h ; 80h (80h) + (82h) + c adc 80h,83h ; 80h (80h) + (83h) + c adc 80h,84h ; 80h (80h) + (84h) + c adc 80h,85h ; 80h (80h) + (85h) + c now, the sum of the six registers is also located in regi ster 80h. however, this instru ction string takes 15 bytes of instruction code rather than 12 by tes, and its execution time is 50 cycles rather than 36 cycles. s3c84bb/f84bb address spaces 2-11 register addressing the s3c8-series register architecture provides an effici ent method of working register addressing that takes full advantage of shorter instruction form ats to reduce execution time. with register (r) addressing mode, in which the operand value is the content of a specif ic register or register pair, you can access any location in the register file except for set 2. with working register addressing, you use a register pointer to specify an 8-byte wo rking register space in the register file and an 8-bit register within that space. registers are addressed either as a single 8-bit register or as a paired 16-bit register space. in a 16-bit register pair, the address of the first 8-bit register is always an even number and the address of t he next register is always an odd number. the most significant byte of the 16-bit data is always stored in the even-numbered register, and the least significant byte is always st ored in the next (+1) odd-numbered register. working register addressing differs from register addressing as it uses a register point er to identify a specific 8-byte working register space in the internal register file and a specific 8-bit register within that space. msb rn lsb rn+1 n = even address figure 2-8. 16-bit register pair address spaces s3c84bb/f84bb 2-12 rp1 rp0 register pointers 00h all addressing modes page 0-7 indirect register, indexed addressing modes page 0-7 register addressing only can be pointed by register pointer ffh e0h bfh control registers system registers special-purpose registers d0h c0h bank 1 bank 0 note: in the s3c84bb/f84bb microcontroller, pages 0-7 are implemented. pages 0-7 contain all of the addressable registers in the internal register file. each register pointer (rp) can independently point to one of the 24 8-byte "slices" of the register file (other than set 2). after a reset, rp0 points to locations c0h-c7h and rp1 to locations c8h-cfh (that is, to the common working register area). ffh c0h set 2 cfh general-purpose register prime registers figure 2-9. register file addressing s3c84bb/f84bb address spaces 2-13 common working register area (c0h?cfh) after a reset, register pointers rp0 and rp 1 automatically select two 8-byte r egister slices in set 1, locations c0h?cfh, as the active 16-byte working register block: rp0 c0h?c7h rp1 c8h?cfh this 16-byte address range is called common area . that is, locations in this area can be used as working registers by operations that address any location on any page in the regist er file. typically, these working registers serve as temporary buffers for data operations between different pages. ffh page 7 ffh f0h e0h d0h c0h set 1 ffh ffh c0h set 2 00h prime space bfh ... page 0 page 0 following a hardware reset, register pointers rp0 and rp1 point to the common working register area, locations c0h-cfh. rp0 = rp1 = 1 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 ~ ~ ~ ~ figure 2-10. common working register area address spaces s3c84bb/f84bb 2-14 programming tip ? addressing the common working register area as the following examples show, you should access worki ng registers in the common area, locations c0h?cfh, using working register addressing mode only. examples 1 : ld 0c2h,40h ; invalid addressing mode! use working register addressing instead: srp #0c0h ld r2,40h ; r2 (c2h) the value in location 40h examples 2: add 0c3h,#45h ; invalid addressing mode! use working register addressing instead: srp #0c0h add r3,#45h ; r3 (c3h) r3 + 45h 4-bit working register addressing each register pointer defines a movable 8-byte slice of working register space. the address information stored in a register pointer serves as an addressing "window" that makes it possible for instructions to access working registers very efficiently using short 4-bit addresses. when an instruction addresses a location in the selected working register area, the address bits are concatenated in the following way to form a complete 8-bit address: ? the high-order bit of the 4-bit address selects one of the register pointers ("0" sele cts rp0, "1" selects rp1). ? the five high-order bits in the register pointer select an 8-byte slice of the register space. ? the three low-order bits of the 4-bit address se lect one of the eight registers in the slice. as shown in figure 2-11, the result of this operation is that the five high-order bits from the register pointer are concatenated with the three low-order bits from the instru ction address to form the complete address. as long as the address stored in the register pointer remains unchanged, the three bits from the address will always point to an address in the same 8-byte register slice. figure 2-12 shows a typical example of 4-bit working regi ster addressing. the high-order bit of the instruction "inc r6" is "0", which selects rp0. the five high-or der bits stored in rp0 (01110b) are concatenated with the three low-order bits of the instruction's 4-bit addr ess (110b) to produce the register address 76h (01110110b). s3c84bb/f84bb address spaces 2-15 together they create an 8-bit register address register pointer provides five high-order bits address opcode selects rp0 or rp1 rp1 rp0 4-bit address provides three low-order bits figure 2-11. 4-bit working register addressing register address (76h) rp0 0 1 1 1 0 0 0 0 0 1 1 1 0 1 1 0 r6 0 1 1 0 1 1 1 0 selects rp0 instruction 'inc r6' opcode rp1 0 1 1 1 1 0 0 0 figure 2-12. 4-bit working register addressing example address spaces s3c84bb/f84bb 2-16 8-bit working register addressing you can also use 8-bit working register addressing to a ccess registers in a selected working register area. to initiate 8-bit working register addressing, the upper four bits of the instruction addr ess must contain the value "1100b." this 4-bit value (1100b) indicates that the remain ing four bits have the same effect as 4-bit working register addressing. as shown in figure 2-13, the lower nibble of the 8-bit addr ess is concatenated in much the same way as for 4-bit addressing. bit 3 selects either rp0 or rp1, which then supplies the five high- order bits of the final address, the three low-order bits of the complete address are provided by the original instruction. figure 2-14 shows an example of 8-bit working register addr essing. the four high-order bits of the instruction address (1100b) specify 8-bit working register addressing. bi t 3 ("1") selects rp1 and the five high-order bits in rp1 (10101b) become the five high-order bits of the regist er address. the three low-order bits of the register address (011) are provided by the three low-order bits of the 8-bit instruction address. the five address bits from rp1 and the three address bits from the instruction are concatenated to form the complete register address, 0abh (10101011b). 8-bit logical address 8-bit physical address register pointer provides five high-order bits address selects rp0 or rp1 rp1 rp0 three low-order bits these address bits indicate 8-bit working register addressing 1100 figure 2-13. 8-bit working register addressing s3c84bb/f84bb address spaces 2-17 8-bit address form instruction 'ld r11, r2' rp0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 selects rp1 r11 register address (0abh) rp1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 specifies working register addressing figure 2-14. 8-bit working register addressing example address spaces s3c84bb/f84bb 2-18 system and user stack the s3c8-series microcontrollers use the system stack for dat a storage, subroutine calls and returns. the push and pop instructions are used to control system sta ck operations. the s3c84bb/f 84bb architecture supports stack operations in the internal register file. stack operations return addresses for procedure calls, interrupts, and data are stored on the stack. t he contents of the pc are saved to stack by a call instruction and restored by the ret instruction. when an interrupt occurs, the contents of the pc and the flags registers are pushed to the stack. the iret instruction then pops these values back to their original locations. the stack address value is always decreased by one before a push operation and increased by one after a pop operation. the stack pointer (sp) always points to the stack frame stored on the top of the stack, as shown in figure 2-15. stack contents after a call instruction stack contents after an interrupt top of stack flags pch pcl pcl pch top of stack low address high address figure 2-15. stack operations user-defined stacks you can freely define stacks in the internal register f ile as data storage locations. the instructions pushui, pushud, popui, and popud support user-defined stack operations. stack pointers (spl, sph) register locations d8h and d9h contain the 16-bit stack poi nter (sp) that is used fo r system stack operations. the most significant byte of the sp address, sp15?sp8, is stored in the sph register (d8h), and the least significant byte, sp7?sp0, is stored in the spl regist er (d9h). after a reset, the sp value is undetermined. because only internal memory space is implemented in the s3c84bb/f84bb, the spl must be initialized to an 8- bit value in the range 00h?ffh. the sph register is not needed and can be used as a general-purpose register, if necessary. when the spl register contains the only stack pointer va lue (that is, when it points to a system stack in the register file), you can use the sph register as a gener al-purpose data register. however, if an overflow or underflow condition occurs as a result of increasing or decreasing the stack address value in the spl register during normal stack operations, the value in the spl regi ster will overflow (or underfl ow) to the sph register, overwriting any other data that is curr ently stored there. to avoid overwrit ing data in the sph register, you can initialize the spl value to "ffh" instead of "00h". s3c84bb/f84bb address spaces 2-19 programming tip ? standard stack operations using push and pop the following example shows you how to perform stack operat ions in the internal register file using push and pop instructions: ld spl,#0ffh ; spl ffh ; (normally, the spl is set to 0ffh by the initialization ; routine) ? ? ? push pp ; stack address 0feh pp push rp0 ; stack address 0fdh rp0 push rp1 ; stack address 0fch rp1 push r3 ; stack address 0fbh r3 ? ? ? pop r3 ; r3 stack address 0fbh pop rp1 ; rp1 stack address 0fch pop rp0 ; rp0 stack address 0fdh pop pp ; pp stack address 0feh address spaces s3c84bb/f84bb 2-20 notes s3c84bb/f84bb addressing modes 3-1 addressing modes overview instructions that are stored in program memory are fetched for execution using the program counter. instructions indicate the operation to be performed and the data to be operated on. addressing mode is the method used to determine the location of the data operand. the operands specified in sam88rc instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. the s3c8-series instruction set supports seven explicit addressing modes. not all of these addressing modes are available for each instruction. the seven addressing modes and their symbols are: ? register (r) ? indirect register (ir) ? indexed (x) ? direct address (da) ? indirect address (ia) ? relative address (ra) ? immediate (im) addressing modes s3c84bb/f84bb 3-2 register addressing mode (r) in register addressing mode (r), the operand value is the content of a specified register or register pair (see figure 3-1). working register addressing differs from register addressing in that it uses a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space (see figure 3-2). dst value used in instruction execution opcode operand 8-bit register file address point to one register in register file one-operand instruction (example) sample instruction: dec cntr ; where cntr is the label of an 8-bit register address program memory register file figure 3-1. register addressing dst opcode 4-bit working register point to the working register (1 of 8) two-operand instruction (example) sample instruction: add r1, r2 ; where r1 and r2 are registers in the currently selected working register area. program memory register file src 3 lsbs rp0 or rp1 selected rp points to start of working register block operand msb point to rp0 ot rp1 figure 3-2. working register addressing s3c84bb/f84bb addressing modes 3-3 indirect register addressing mode (ir) in indirect register (ir) addressing mode, the content of the specified register or register pair is the address of the operand. depending on the instruction used, the actual address may point to a register in the register file, to program memory (rom), or to an external memory space (see figures 3-3 through 3-6). you can use any 8-bit register to indirectly address another register. any 16-bit register pair can be used to indirectly address another memory location. please note, however, that you cannot access locations c0h?ffh in set 1 using the indirect register addressing mode. dst address of operand used by instruction opcode address 8-bit register file address point to one register in register file one-operand instruction (example) sample instruction: rl @shift ; where shift is the label of an 8-bit register address program memory register file value used in instruction execution operand figure 3-3. indirect register addressing to register file addressing modes s3c84bb/f84bb 3-4 indirect register addressing mode (continued) dst opcode pair points to register pair example instruction references program memory sample instructions: call @rr2 jp @rr2 program memory register file value used in instruction operand register program memory 16-bit address points to program memory figure 3-4. indirect register addressing to program memory s3c84bb/f84bb addressing modes 3-5 indirect register addressing mode (continued) dst opcode address 4-bit working register address point to the working register (1 of 8) sample instruction: or r3, @r6 program memory register file src 3 lsbs value used in instruction operand selected rp points to start fo working register block rp0 or rp1 msb points to rp0 or rp1 ~~ ~~ figure 3-5. indirect working register addressing to register file addressing modes s3c84bb/f84bb 3-6 indirect register addressing mode (concluded) dst opcode 4-bit w orking register address sample instructions: ldc r5,@rr6 ; program memory access lde r3,@ rr14 ; external data m em ory access lde @ rr4, r8 ; external data m em ory access program memory r egister file src value used in instruction operand example instruction references either program memory or data mem ory program memory or data mem ory next 2-bit point to w orking register pair (1 of 4) lsb selects register pair 16-bit address points to program memory or data memory rp0 or rp1 msb points to rp0 or rp1 selected rp points to start of working register block figure 3-6. indirect working register addressing to program or data memory s3c84bb/f84bb addressing modes 3-7 indexed addressing mode (x) indexed (x) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see figure 3-7). you can use indexed addressing mode to access locations in the internal register file or in external memory. please note, however, that you cannot access locations c0h?ffh in set 1 using indexed addressing mode. in short offset indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range ?128 to +127. this applies to external memory accesses only (see figure 3-8.) for register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in a working register. for external memory accesses, the base address is stored in the working register pair designated in the instruction. the 8-bit or 16-bit offset given in the instruction is then added to that base address (see figure 3-9). the only instruction that supports indexed addressing mode for the internal register file is the load instruction (ld). the ldc and lde instructions support indexed addressing mode for internal program memory and for external data memory, when implemented. dst/src opcode two-operand instruction example point to one of the w orking register (1 of 8) sample instruction: ld r0, #base[r1] ; w here base is an 8-bit immediate value program memory register file x 3 lsbs value used in instruction operand index base address rp0 or rp1 selected rp points to start of working register block + figure 3-7. indexed addressing to register file addressing modes s3c84bb/f84bb 3-8 indexed addressing mode (continued) register file operand program memory or data memory point to working register pair (1 of 4) lsb selects 16-bit address added to offset rp0 or rp1 msb points to rp0 or rp1 selected rp points to start of working register block dst/src opcode program memory x offset 4-bit working register address sample instructions: ldc r4, #04h[rr2] ; the values in the program address (rr2 + 04h) are loaded into register r4. lde r4,#04h[rr2] ; identical operation to ldc example, except that external program memory is accessed. next 2 bits register pair value used in instruction 8-bits 16-bits 16-bits + ~~ figure 3-8. indexed addressing to program or data memory with short offset s3c84bb/f84bb addressing modes 3-9 indexed addressing mode (continued) register file operand program memory or data memory point to working register pair lsb selects 16-bit address added to offset rp0 or rp1 msb points to rp0 or rp1 selected rp points to start of working register block sample instructions: ldc r4, #1000h[rr2] ; the values in the program address (rr2 + 1000h) are loaded into register r4. lde r4,#1000h[rr2] ; identical operation to ldc example, except that external program memory is accessed. next 2 bits register pair value used in instruction 16-bits 16-bits 16-bits dst/src opcode program memory src offset 4-bit working register address offset + ~~ figure 3-9. indexed addressing to program or data memory addressing modes s3c84bb/f84bb 3-10 direct address mode (da) in direct address (da) mode, the instruction provides the operand's 16-bit memory address. jump (jp) and call (call) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the pc whenever a jp or call instruction is executed. the ldc and lde instructions can use direct address mode to specify the source or destination address for load operations to program memory (ldc) or to external data memory (lde), if implemented. sample instructions: ldc r5,1234h ; the values in the program address (1234h) are loaded into register r5. lde r5,1234h ; identical operation to ldc example, except that external program memory is accessed. dst/src opcode program memory "0" or "1" lower address byte lsb selects program memory or data memory: "0" = program memory "1" = data memory memory address used upper address byte program or data memory figure 3-10. direct addressing for load instructions s3c84bb/f84bb addressing modes 3-11 direct address mode (continued) opcode program memory lower address byte memory address used upper address byte sample instructions: jp c,job1 ; where job1 is a 16-bit immediate address call display ; where display is a 16-bit immediate address next opcode figure 3-11. direct addressing for call and jump instructions addressing modes s3c84bb/f84bb 3-12 indirect address mode (ia) in indirect address (ia) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. the selected pair of memory locations contains the actual address of the next instruction to be executed. only the call instruction can use the indirect address mode. because the indirect address mode assumes that the operand is located in the lowest 256 bytes of program memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are assumed to be all zeros. current instruction program memory locations 0-255 program memory opcode dst lower address byte upper address byte next instruction lsb must be zero sample instruction: call #40h ; the 16-bit value in program memory addresses 40h and 41h is the subroutine start address. figure 3-12. indirect addressing s3c84bb/f84bb addressing modes 3-13 relative address mode (ra) in relative address (ra) mode, a twos-complement signed displacement between ? 128 and + 127 is specified in the instruction. the displacement value is then added to the current pc value. the result is the address of the next instruction to be executed. before this addition occurs, the pc contains the address of the instruction immediately following the current instruction. several program control instructions use the relative address mode to perform conditional jumps. the instructions that support ra addressing are btjrf, btjrt, djnz, cpije, cpijne, and jr. opcode program memory displacement program memory address used sample instructions: jr ult,$+offset ; where offset is a value in the range +127 to -128 next opcode + signed displacement value current instruction current pc value figure 3-13. relative addressing addressing modes s3c84bb/f84bb 3-14 immediate mode (im) in immediate (im) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. the operand may be one byte or one word in length, depending on the instruction used. immediate addressing mode is useful for loading constant values into registers. (the operand value is in the instruction) opcode sample instruction: ld r0,#0aah program memory operand figure 3-14. immediate addressing s3c84bb/f84bb control registers 4-1 control registers overview control register descriptions are arranged in alphabetical order according to register mnemonic. more detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in part ii of this manual. the locations and read/write characteristics of all mapped registers in the s3c84bb/f84bb register file are listed in table 4-1. the hardware reset value for each mapped register is described in chapter 8, ? reset and power- down." table 4-1. set 1 registers register name mnemonic decimal hex r/w timer b control register tbcon 208 d0h r/w timer b data register (high byte) tbdatah 209 d1h r/w timer b data register (low byte) tbdatal 210 d2h r/w basic timer control register btcon 211 d3h r/w clock control register clkcon 212 d4h r/w system flags register flags 213 d5h r/w register pointer 0 rp0 214 d6h r/w register pointer 1 rp1 215 d7h r/w stack pointer (high byte) sph 216 d8h r/w stack pointer (low byte) spl 217 d9h r/w instruction pointer (high byte) iph 218 dah r/w instruction pointer (low byte) ipl 219 dbh r/w interrupt request register irq 220 dch r interrupt mask register imr 221 ddh r/w system mode register sym 222 deh r/w register page pointer pp 223 dfh r/w control registers s3c84bb/f84bb 4-2 table 4-2. set 1, bank 0 registers register name mnemonic decimal hex r/w port 0 data register p0 224 e0h r/w port 1 data register p1 225 e1h r/w port 2 data register p2 226 e2h r/w port 3 data register p3 227 e3h r/w port 4 data register p4 228 e4h r/w port 5 data register p5 229 e5h r/w port 6 data register p6 230 e6h r/w port 7 data register p7 231 e7h r/w port 8 data register p8 232 e8h r/w timer a/1 interrupt pending register tintpnd 233 e9h r/w timer a control register tacon 234 eah r/w timer a data register tadata 235 ebh r/w timer a counter register tacnt 236 ech r port 8 control register (high byte) p8conh 237 edh r/w port 8 control register (low byte) p8conl 238 eeh r/w port 8 interrupt/pending register p8intpnd 239 efh r/w port 0 control register p0con 240 f0h r/w port 1 control register p1con 241 f1h r/w port 2 control register (high byte) p2conh 242 f2h r/w port 2 control register (low byte) p2conl 243 f3h r/w port 3 control register (high byte) p3conh 244 f4h r/w port 3 control register (low byte) p3conl 245 f5h r/w port 4 control register (high byte) p4conh 246 f6h r/w port 4 control register (low byte) p4conl 247 f7h r/w port 5 control register (high byte) p5conh 248 f8h r/w port 5 control register (low byte) p5conl 249 f9h r/w port 4 interrupt control register p4int 250 fah r/w port 4 interrupt/pending register p4intpnd 251 fbh r/w location fch is factory use only basic timer counter register btcnt 253 fdh r location feh is not mapped. interrupt priority register ipr 255 ffh r/w s3c84bb/f84bb control registers 4-3 table 4-3. set 1, bank 1 registers register name mnemonic decimal hex r/w sio data register siodata 224 e0h r/w sio control register siocon 225 e1h r/w uart0 data register udata0 226 e2h r/w uart0 control register uartcon0 227 e3h r/w uart0 baud rate data register brdata0 228 e4h r/w uart0,1 pending register uartpnd 229 e5h r/w timer 1(0) data register (high byte) t1datah0 230 e6h r/w timer 1(0) data register (low byte) t1datal0 231 e7h r/w timer 1(1) data register (high byte) t1datah1 232 e8h r/w timer 1(1) data register (low byte) t1datal1 233 e9h r/w timer 1(0) control register t1con0 234 eah r/w timer 1(1) control register t1con1 235 ebh r/w timer 1(0) counter register (high byte) t1cnth0 236 ech r timer 1(0) counter register (low byte) t1cntl0 237 edh r timer 1(1) counter register (high byte) t1cnth1 238 eeh r timer 1(1) counter register (low byte) t1cntl1 239 efh r timer c(0) data register tcdata0 240 f0h r/w timer c(1) data register tcdata1 241 f1h r/w timer c(0) control register tccon0 242 f2h r/w timer c(1) control register tccon1 243 f3h r/w sio prescaler control register siops 244 f4h r/w port 7 control register p7con 245 f5h r/w d/a converter data register dadata 246 f6h r/w a/d, d/a converter control register adacon 247 f7h r/w a/d converter data register (high byte) addatah 248 f8h r a/d converter data register (low byte) addatal 249 f9h r uart1 data register udata1 250 fah r/w uart1 control register uartcon1 251 fbh r/w uart1 baud rate data register brdata1 252 fch r/w flash memory control register fmcon 253 fdh r/w pattern generation control register pgcon 254 feh r/w pattern generation data register pgdata 255 ffh r/w control registers s3c84bb/f84bb 4-4 flags - system flags register .7 carry flag (c) .6 zero flag (z) .5 bit identifier reset value read/write bit addressing mode r = read-only w = write-only r/w = read/write '-' = not used type of addressing that must be used to address the bit (1-bit, 4-bit, or 8-bit) reset value notation: '-' = not used 'x' = undetermined value '0' = logic zero '1' = logic one bit number(s) that is/are appended to the register name for bit addressing name of individual bit or related bits register name register id sign flag (s) 0 operation does not generate a carry or borrow condition 0 operation generates carry-out or borrow into high-order bit 7 0 operation result is a non-zero value 0 operation result is zero 0 operation generates positive number (msb = "0") 0 operation generates negative number (msb = "1") description of the effect of specific bit settings set 1 register location in the internal register file d5h register address (hexadecimal) .7 .6 .5 x r/w register addressing mode only .4 .3 .2 bit number: msb = bit 7 lsb = bit 0 .1 .0 x r/w x r/w x r/w x r/w x r/w 0 r 0 r/w figure 4-1. register description format s3c84bb/f84bb control registers 4-5 adacon ? a/d, d/a converter control register f7h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r r/w r/w r/w addressing mode register addressing mode only .7 d/a start enable bit 0 disable operation 1 start operation .6-.4 a/d input pin selection bits 0 0 0 adc0 0 0 1 adc1 0 1 0 adc2 0 1 1 adc3 1 0 0 adc4 1 0 1 adc5 1 1 0 adc6 1 1 1 adc7 .3 end-of-conversion bit (read-only) 0 a/d conversion opration is in progress 1 a/d conversion opration is complete .2-.1 clock source selection bits 0 0 fxx/16 0 1 fxx/8 1 0 fxx/4 1 1 fxx .0 a/d start or enable bit 0 disable operation 1 start operation control registers s3c84bb/f84bb 4-6 brdata0 ? uart0 baud rate data register e4h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 baud rate data for uart0 (note) : fxx/(16 (brdata + 1)) note: refer to uartcon0 register. s3c84bb/f84bb control registers 4-7 brdata1 ? uart1 baud rate data register fch set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 1 1 1 1 1 1 1 1 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 baud rate data for uart1 (note) : fxx/(16 (brdata + 1)) note: refer to uartcon1 register. control registers s3c84bb/f84bb 4-8 btcon ? basic timer control register d3h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7-.4 watchdog timer function disable code (for system reset) 1 0 1 0 disable watchdog timer function others enable watchdog timer function .3-.2 basic timer input clock selection bits 0 0 fxx/4096 (3) 0 1 fxx/1024 1 0 fxx/128 1 1 fxx/16 (not used) .1 basic timer counter clear bit (1) 0 no effect 1 clear the basic timer counter value .0 clock frequency divider clear bit for basic timer (2) 0 no effect 1 clear both clock frequency dividers notes: 1. when you write a ?1? to btcon.1, the basic timer counter value is cleared to "00h". immediately following the write operation, the btcon.1 value is automatically cleared to ?0?. 2. when you write a "1" to btcon.0, the corresponding frequency divider is cleared to "00h". immediately following the write operation, the btcon.0 value is automatically cleared to "0". 3. the fxx is selected clock for system (main osc. or sub osc.). s3c84bb/f84bb control registers 4-9 clkcon ? system clock control register d4h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write ? ? ? r/w r/w ? ? ? addressing mode register addressing mode only .7-.5 not used for the s3c84bb/f84bb (must keep always 0) .4-.3 cpu clock (system clock) selection bits (note) 0 0 fxx/16 0 1 fxx/8 1 0 fxx/2 1 1 fxx/1 (non-divided) .2-.0 not used for the s3c84bb/f84bb (must keep always 0) note: after a reset, the slowest clock (divided by 16) is selected as the system clock. to select faster clock speeds, load the appropriate values to clkcon.3 and clkcon.4. control registers s3c84bb/f84bb 4-10 flags ? system flags register d5h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value x x x x x x 0 0 read/write r/w r/w r/w r/w r/w r/w r r/w addressing mode register addressing mode only .7 carry flag (c) 0 operation does not generate a carry or underflow condition 1 operation generates a carry-out or underflow into high-order bit 7 .6 zero flag (z) 0 operation result is a non-zero value 1 operation result is zero .5 sign flag (s) 0 operation generates a positive number (msb = "0") 1 operation generates a negative number (msb = "1") .4 overflow flag (v) 0 operation result is +127 or ?128 1 operation result is > +127 or < ?128 .3 decimal adjust flag (d) 0 add operation completed 1 subtraction operation completed .2 half-carry flag (h) 0 no carry-out of bit 3 or no underflow into bit 3 by addition or subtraction 1 addition generated carry-out of bit 3 or subtraction generated underflow into bit 3 .1 fast interrupt status flag (fis) 0 interrupt return (iret) in progress (when read) 1 fast interrupt service routine in progress (when read) .0 bank address selection flag (ba) 0 bank 0 is selected 1 bank 1 is selected s3c84bb/f84bb control registers 4-11 fmcon ? flash memory control register fdh set 1, bank1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w ? ? ? ? ? r/w r/w addressing mode register addressing mode only .7 user programming serial data bit (fsdat) 0 fsda=low (logic 0) 1 fsda=high (logic 1) .6-.2 not used for the s3c84bb/f84bb (must keep always 0) .1 user programming mode status bit (full-flash flag) 0 not-user programming mode 1 user programming mode .0 user programming serial clock bit (fsclk) 0 fsclk=low (logic 0) 1 fsclk=high(logic 1) control registers s3c84bb/f84bb 4-12 imr ? interrupt mask register ddh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 interrupt level 7 (irq7) enable bit 0 disable (mask) 1 enable (un-mask) .6 interrupt level 6 (irq6) enable bit 0 disable (mask) 1 enable (un-mask) .5 interrupt level 5 (irq5) enable bit 0 disable (mask) 1 enable (un-mask) .4 interrupt level 4 (irq4) enable bit 0 disable (mask) 1 enable (un-mask) .3 interrupt level 3 (irq3) enable bit 0 disable (mask) 1 enable (un-mask) .2 interrupt level 2 (irq2) enable bit 0 disable (mask) 1 enable (un-mask) .1 interrupt level 1 (irq1) enable bit 0 disable (mask) 1 enable (un-mask) .0 interrupt level 0 (irq0) enable bit 0 disable (mask) 1 enable (un-mask) note: when an interrupt level is masked, any interrupt requests that may be issued are not recognized by the cpu. s3c84bb/f84bb control registers 4-13 iph ? instruction pointer (high byte) dah set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 instruction pointer address (high byte) the high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (ip15?ip8). the lower byte of the ip address is located in the ipl register (dbh). ipl ? instruction pointer (low byte) dbh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 instruction pointer address (low byte) the low-byte instruction pointer value is the lower eight bits of the 16-bit instruction pointer address (ip7?ip0). the upper byte of the ip address is located in the iph register (dah). control registers s3c84bb/f84bb 4-14 ipr ? interrupt priority register ffh set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7, .4, and .1 priority control bits for interrupt groups a, b, and c 0 0 0 group priority undefined 0 0 1 b > c > a 0 1 0 a > b > c 0 1 1 b > a > c 1 0 0 c > a > b 1 0 1 c > b > a 1 1 0 a > c > b 1 1 1 group priority undefined .6 interrupt subgroup c priority control bit 0 irq6 > irq7 1 irq7 > irq6 .5 interrupt group c priority control bit 0 irq5 > (irq6, irq7) 1 (irq6, irq7) > irq5 .3 interrupt subgroup b priority control bit 0 irq3 > irq4 1 irq4 > irq3 .2 interrupt group b priority control bit 0 irq2 > (irq3, irq4) 1 (irq3, irq4) > irq2 .0 interrupt group a priority control bit 0 irq0 > irq1 1 irq1 > irq0 s3c84bb/f84bb control registers 4-15 irq ? interrupt request register dch set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r r r r r r r r addressing mode register addressing mode only .7 level 7 (irq7) request pending bit 0 not pending 1 pending .6 level 6 (irq6) request pending bit 0 not pending 1 pending .5 level 5 (irq5) request pending bit 0 not pending 1 pending .4 level 4 (irq4) request pending bit 0 not pending 1 pending .3 level 3 (irq3) request pending bit 0 not pending 1 pending .2 level 2 (irq2) request pending bit 0 not pending 1 pending .1 level 1 (irq1) request pending bit 0 not pending 1 pending .0 level 0 (irq0) request pending bit 0 not pending 1 pending control registers s3c84bb/f84bb 4-16 p0con ? port 0 control register f0h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7-.6 p0.7/p0.6/p0.5/p0.4 0 0 input mode 0 1 input mode, pull-up 1 0 push-pull output 1 1 alternative function mode (pgout<7:4>) .5?.4 p0.3/p0.2 0 0 input mode 0 1 input mode, pull-up 1 0 push-pull output 1 1 alternative function mode (pgout<3:2>) .3?.2 p0.1 0 0 input mode 0 1 input mode, pull-up 1 0 push-pull output 1 1 alternative function mode (pgout<1>) .1?.0 p0.0 0 0 input mode 0 1 input mode, pull-up 1 0 push-pull output 1 1 alternative function mode (pgout<0>) s3c84bb/f84bb control registers 4-17 p1con ? port 1 control register f1h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 p1.7/p1.6 0 0 input mode 0 1 input mode, pull-up 1 x push-pull output .5?.4 p1.5/p1.4 0 0 input mode 0 1 input mode, pull-up 1 x push-pull output .3?.2 p1.3/p1.2 0 0 input mode 0 1 input mode, pull-up 1 x push-pull output .1?.0 p1.1/p1.0 0 0 input mode 0 1 input mode, pull-up 1 x push-pull output control registers s3c84bb/f84bb 4-18 p2conh ? port 2 control register (high byte) f2h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 p2.7/taout 0 0 input mode 0 1 input mode, pull-up 1 0 push-pull output 1 1 alternative output mode(taout) .5-.4 p2.6/tacap 0 0 input mode(tacap) 0 1 input mode, pull-up(tacap) 1 0 push-pull output 1 1 alternative output mode(not used) .3?.2 p2.5/tack 0 0 input mode(tack) 0 1 input mode, pull-up(tack) 1 0 push-pull output 1 1 alternative output mode(not used) .1?.0 p2.4/ tbpwm 0 0 input mode 0 1 input mode, pull-up 1 0 push-pull output 1 1 alternative output mode(tbpwm) s3c84bb/f84bb control registers 4-19 p2conl ? port 2 control register (low byte) f3h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7-.6 p2.3/daout 0 0 input mode 0 1 input mode, pull-up 1 0 push-pull output 1 1 alternative output mode (daout) .5-.4 p2.2/sck 0 0 input mode (sck input) 0 1 input mode, pull-up (sck input) 1 0 push-pull output 1 1 alternative output mode (sck output) .3-.2 p2.1/si 0 0 input mode(si) 0 1 input mode, pull-up(si) 1 0 push-pull output 1 1 alternative output mode(not used) .1-.0 p2.0/so 0 0 input mode 0 1 input mode, pull-up 1 0 push-pull output 1 1 alternative output mode (so) control registers s3c84bb/f84bb 4-20 p3conh ? port 3 control register (high byte) f4h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 p3.7/tcout1 0 0 input mode 0 1 input mode, pull-up 1 0 push-pull output 1 1 alternative output mode(tcout1) .5-.4 p3.6/tcout0 0 0 input mode 0 1 input mode, pull-up 1 0 push-pull output 1 1 alternative output mode(tcout0) .3?.2 p3.5/ t1out1 0 0 input mode 0 1 input mode, pull-up 1 0 push-pull output 1 1 alternative output mode(t1out1) .1?.0 p3.4/ t1out0 0 0 input mode 0 1 input mode, pull-up 1 0 push-pull output 1 1 alternative output mode(t1out0) s3c84bb/f84bb control registers 4-21 p3conl ? port 3 control register (low byte) f5h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7-.6 p3.3/t1cap1 0 0 input mode (t1cap1) 0 1 input mode, pull-up (t1cap1) 1 x push-pull output .5-.4 p3.2/ t1cap0 0 0 input mode (t1cap0) 0 1 input mode, pull-up (t1cap0) 1 x push-pull output .3-.3 p3.1/t1ck1 0 0 input mode (t1ck1) 0 1 input mode, pull-up (t1ck1) 1 x push-pull output .1-.0 p3.0/t1ck0 0 0 input mode (t1ck0) 0 1 input mode, pull-up (t1ck0) 1 x push-pull output control registers s3c84bb/f84bb 4-22 p4conh ? port 4 control register (high byte) f6h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 p4.7/int7 0 0 input mode; falling edge interrupt 0 1 input mode; rising edge interrupt 1 0 input mode, pull-up; falling edge interrupt 1 1 push-pull output .5-.4 p4.6/ int6 0 0 input mode; falling edge interrupt 0 1 input mode; rising edge interrupt 1 0 input mode, pull-up; falling edge interrupt 1 1 push-pull output .3?.2 p4.5/ int5 0 0 input mode; falling edge interrupt 0 1 input mode; rising edge interrupt 1 0 input mode, pull-up; falling edge interrupt 1 1 push-pull output .1?.0 p4.4/ int4 0 0 input mode; falling edge interrupt 0 1 input mode; rising edge interrupt 1 0 input mode, pull-up; falling edge interrupt 1 1 push-pull output s3c84bb/f84bb control registers 4-23 p4conl ? port 4 control register (low byte) f7h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7-.6 p4.3/int3 0 0 input mode; falling edge interrupt 0 1 input mode; rising edge interrupt 1 0 input mode, pull-up; falling edge interrupt 1 1 push-pull output .5-.4 p4.2/int2 0 0 input mode; falling edge interrupt 0 1 input mode; rising edge interrupt 1 0 input mode, pull-up; falling edge interrupt 1 1 push-pull output .3-.2 p4.1/int1 0 0 input mode; falling edge interrupt 0 1 input mode; rising edge interrupt 1 0 input mode, pull-up; falling edge interrupt 1 1 push-pull output .1-.0 p4.0/int0 0 0 input mode; falling edge interrupt 0 1 input mode; rising edge interrupt 1 0 input mode, pull-up; falling edge interrupt 1 1 push-pull output control registers s3c84bb/f84bb 4-24 p4int ? port 4 interrupt control register fah set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 p4.7 external interrupt (int7) enable bit 0 disable interrupt 1 enable interrupt .6 p4.6 external interrupt (int6) enable bit 0 disable interrupt 1 enable interrupt .5 p4.5 external interrupt (int5) enable bit 0 disable interrupt 1 enable interrupt .4 p4.4 external interrupt (int4) enable bit 0 disable interrupt 1 enable interrupt .3 p4.3 external interrupt (int3) enable bit 0 disable interrupt 1 enable interrupt .2 p4.2 external interrupt (int2) enable bit 0 disable interrupt 1 enable interrupt .1 p4.1 external interrupt (int1) enable bit 0 disable interrupt 1 enable interrupt .0 p4.0 external interrupt (int0) enable bit 0 disable interrupt 1 enable interrupt s3c84bb/f84bb control registers 4-25 p4intpnd ? port 4 interrupt pending register fbh set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 p4.7/int7 interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending .6 p4.6/int6 interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending .5 p4.5/int5 interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending .4 p4.4/int4 interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending .3 p4.3/int3 interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending .2 p4.2/int2 interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending .1 p4.1/int1 interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending .0 p4.0/int0 interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending control registers s3c84bb/f84bb 4-26 p5conh ? port 5 control register (high byte) f8h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 p5.7 0 0 input mode 0 1 input mode, pull-up 1 0 push-pull output 1 1 open-drain mode .5-.4 p5.6 0 0 input mode 0 1 input mode, pull-up 1 0 push-pull output 1 1 open-drain mode .3?.2 p5.5 0 0 input mode 0 1 input mode, pull-up 1 0 push-pull output 1 1 open-drain mode .1?.0 p5.4 0 0 input mode 0 1 input mode, pull-up 1 0 push-pull output 1 1 open-drain mode s3c84bb/f84bb control registers 4-27 p5conl ? port 5 control register (low byte) f9h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7-.6 p5.3/rxd0 0 0 input mode (rxd0 input) 0 1 input mode, pull-up mode (rxd0 input) 1 0 push-pull output 1 1 alternative output mode (rxd0 output) .5-.4 p5.2/txd0 0 0 input mode 0 1 input mode, pull-up mode 1 0 push-pull output 1 1 alternative output mode (txd0 output) .3-.2 p5.1/rxd1 0 0 input mode (rxd1 input) 0 1 input mode, pull-up mode (rxd1 input) 1 0 push-pull output 1 1 alternative output mode (rxd1 output) .1-.0 p5.0/txd1 0 0 input mode 0 1 input mode, pull-up mode 1 0 push-pull output 1 1 alternative output mode (txd1 output) control registers s3c84bb/f84bb 4-28 p7con ? port 7 control register f5h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 p7.7/adc7 0 input mode 1 adc input mode .6 p7.6/ adc6 0 input mode 1 adc input mode .5 p7.5/ adc5 0 input mode 1 adc input mode .4 p7.4/ adc4 0 input mode 1 adc input mode .3 p7.3/ adc3 0 input mode 1 adc input mode .2 p7.2/ adc2 0 input mode 1 adc input mode .1 p7.1/ adc1 0 input mode 1 adc input mode .0 p7.0/ adc0 0 input mode 1 adc input mode s3c84bb/f84bb control registers 4-29 p8conh ? port 8 control register (high byte) edh set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 1 1 1 1 0 0 0 0 read/write -? ? ? ?- r/w r/w r/w r/w addressing mode register addressing mode only .7 ? ? ? ? .4 not used for the s3c84bb/f84bb (must keep always 1) .3?.2 p8.5/ int9 0 0 input mode; falling edge interrupt 0 1 input mode; rising edge interrupt 1 0 input mode, pull-up; falling edge interrupt 1 1 push-pull output .1?.0 p8.4/ int8 0 0 input mode; falling edge interrupt 0 1 input mode; rising edge interrupt 1 0 input mode, pull-up; falling edge interrupt 1 1 push-pull output control registers s3c84bb/f84bb 4-30 p8conl ? port 8 control register (low byte) eeh set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7-.6 p8.3 0 0 input mode 0 1 input mode, pull-up 1 x push-pull output .5-.4 p8.2 0 0 input mode 0 1 input mode, pull-up 1 x push-pull output .3-.2 p8.1 0 0 input mode 0 1 input mode, pull-up 1 x push-pull output .1-.0 p8.0 0 0 input mode 0 1 input mode, pull-up 1 x push-pull output s3c84bb/f84bb control registers 4-31 p8intpnd ? port 8 interrupt pending register efh set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 1 1 0 0 1 1 0 0 read/write ? ? - r/w r/w ? ? r/w r/w addressing mode register addressing mode only .7-.6 not used for the s3c84bb/f84bb (must keep always 1) .5 p8.5/int9 interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending .4 p8.4/int8 interrupt pending bit 0 interrupt request is not pending, pending bit clear when write 0 1 interrupt request is pending .3-.2 not used for the s3c84bb/f84bb (must keep always 1) .1 p8.5/int9 interrupt enable 0 disable interrupt 1 enable interrupt .0 p8.4/int8 interrupt enable 0 disable interrupt 1 enable interrupt control registers s3c84bb/f84bb 4-32 pgcon ? pattern generation control register feh set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w addressing mode register addressing mode only .7-.4 not used for the s3c84bb/f84bb .3 software trigger start bit 0 no effect 1 software trigger start (will be automatically cleared) .2 pg operation disable/enable selection bit 0 pg operation disable 1 pg operation enable .1-.0 pg operation trigger mode selection bits 0 0 timer a match siganal triggering 0 1 timer b underflow siganal triggering 1 0 timer 1(0) match siganal triggering 1 1 software triggering mode s3c84bb/f84bb control registers 4-33 pp ? register page pointer dfh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7-.4 destination register page selection bits 0 0 0 0 destination: page 0 0 0 0 1 destination: page 1 0 0 1 0 destination: page 2 0 0 1 1 destination: page 3 0 1 0 0 destination: page 4 0 1 0 1 destination: page 5 0 1 1 0 destination: page 6 0 1 1 1 destination: page 7 .3-.0 source register page selection bits 0 0 0 0 source: page 0 0 0 0 1 source: page 1 0 0 1 0 source: page 2 0 0 1 1 source: page 3 0 1 0 0 source: page 4 0 1 0 1 source: page 5 0 1 1 0 source: page 6 0 1 1 1 source: page 7 note: in the s3c84bb/f84bb microcontroller, the internal register file is configured as eight pages (pages 0-7). the pages 0-1 are used for general-purpose register file, and page 2-7 is used for data register or general purpose registers. control registers s3c84bb/f84bb 4-34 rp0 ? register pointer 0 d6h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 1 1 0 0 0 ? ? ? read/write r/w r/w r/w r/w r/w ? ? ? addressing mode register addressing only .7-.3 register pointer 0 address value register pointer 0 can independently point to one of the 256-byte working register areas in the register file. using the register pointers rp0 and rp1, you can select two 8-byte register slices at one time as active working register space. after a reset, rp0 points to address c0h in register set 1, selecting the 8-byte working register slice c0h?c7h. .2-.0 not used for the s3c84bb/f84bb rp1 ? register pointer 1 d7h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 1 1 0 0 1 ? ? ? read/write r/w r/w r/w r/w r/w ? ? ? addressing mode register addressing only .7-.3 register pointer 1 address value register pointer 1 can independently point to one of the 256-byte working register areas in the register file. using the register pointers rp0 and rp1, you can select two 8-byte register slices at one time as active working register space. after a reset, rp1 points to address c8h in register set 1, selecting the 8-byte working register slice c8h?cfh. .2-.0 not used for the s3c84bb/f84bb s3c84bb/f84bb control registers 4-35 siocon ? sio control register e1h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 sio shift clock selection bit 0 internal clock (p.s clock) 1 external clock (sck) .6 data direction control bit 0 msb first mode 1 lsb first mode .5 sio mode selection bit 0 receive only mode 1 transmit/receive mode .4 shift start edge selection bit 0 tx at falling edges, rx at rising edges 1 tx at rising edges, rx at falling edges .3 sio counter clear and shift start bit 0 no action 1 clear 3-bit counter and start shifting (auto-clear bit) .2 sio shift operation enable bit 0 disable shifter and clock counter 1 enable shifter and clock counter .1 sio interrupt enable bit 0 disable sio interrupt 1 enable sio interrupt .0 sio interrupt pending bit 0 no interrupt pending 0 clear pending condition (when write) 1 interrupt is pending control registers s3c84bb/f84bb 4-36 siops ? sio prescaler register f4h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 baud rate = input clock (fxx)/[(siops + 1) 2] or sck input clock s3c84bb/f84bb control registers 4-37 sph ? stack pointer (high byte) d8h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 stack pointer address (high byte) the high-byte stack pointer value is the upper eight bits of the 16-bit stack pointer address (sp15?sp8). the lower byte of the stack pointer value is located in register spl (d9h). the sp value is undefined following a reset. spl ? stack pointer (low byte) d9h set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value x x x x x x x x read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.0 stack pointer address (low byte) the low-byte stack pointer value is the lower eight bits of the 16-bit stack pointer address (sp7?sp0). the upper byte of the stack pointer value is located in register sph (d8h). the sp value is undefined following a reset. control registers s3c84bb/f84bb 4-38 sym ? system mode register deh set 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 ? ? x x x 0 0 read/write r/w ? ? r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 not used, but you must keep ?0? .6 and .5 not used for s3c84bb/f84bb .4?.2 fast interrupt level selection bits 0 0 0 irq0 0 0 1 irq1 0 1 0 irg2 0 1 1 irq3 1 0 0 irq4 1 0 1 irq5 1 1 0 irq6 1 1 1 irq7 .1 fast interrupt enable bit 0 disable fast interrupt processing 1 enable fast interrupt processing .0 global interrupt enable bit (note) 0 disable global interrupt processing 1 enable global interrupt processing note : following a reset, you enable global interrupt processing by executing an ei instruction (not by writing a "1" to sym.0). s3c84bb/f84bb control registers 4-39 t1con0 ? timer 1(0) control register eah set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7-.5 timer 1 input clock selection bits 0 0 0 fxx/1024 0 0 1 fxx (non-divide) 0 1 0 fxx/256 0 1 1 external clock falling edge 1 0 0 fxx/64 1 0 1 external clock rising edge 1 1 0 fxx/8 1 1 1 counter stop .4-.3 timer 1 operating mode selection bits 0 0 interval mode 0 1 capture mode (capture on rising edge, ovf can occur) 1 0 capture mode (capture on falling edge, ovf can occur) 1 1 pwm mode .2 timer 1 counter enable bit 0 no effect 1 clear the timer 1 counter (auto-clear bit) .1 timer 1 match/capture interrupt enable bit 0 disable interrupt 1 enable interrupt .0 timer 1 overflow interrupt enable 0 disable overflow interrupt 1 enable overflow interrupt control registers s3c84bb/f84bb 4-40 t1con1 ? timer 1(1) control register ebh set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7-.5 timer 1 input clock selection bits 0 0 0 fxx/1024 0 0 1 fxx (non-divide) 0 1 0 fxx/256 0 1 1 external clock falling edge 1 0 0 fxx/64 1 0 1 external clock rising edge 1 1 0 fxx/8 1 1 1 counter stop .4-.3 timer 1 operating mode selection bits 0 0 interval mode 0 1 capture mode (capture on rising edge, ovf can occur) 1 0 capture mode (capture on falling edge, ovf can occur) 1 1 pwm mode .2 timer 1 counter enable bit 0 no effect 1 clear the timer 1 counter (auto-clear bit) .1 timer 1 match/capture interrupt enable bit 0 disable interrupt 1 enable interrupt .0 timer 1 overflow interrupt enable 0 disable overflow interrupt 1 enable overflow interrupt s3c84bb/f84bb control register 4-41 tacon ? timer a control register eah set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 ? read/write r/w r/w r/w r/w r/w r/w r/w ? addressing mode register addressing mode only .7-.6 timer a input clock selection bits 0 0 fxx/1024 0 1 fxx/256 1 0 fxx/64 1 1 external clock (tack) .5-.4 timer a operating mode selection bits 0 0 interval mode (taout mode) 0 1 capture mode (capture on rising edge, counter running, ovf can occur) 1 0 capture mode (capture on falling edge, counter running, ovf can occur) 1 1 pwm mode (ovf interrupt can occur) .3 timer a counter clear bit 0 no effect 1 clear the timer a counter (after clearing, return to zero) .2 timer a overflow interrupt enable bit 0 disable overflow interrupt 1 enable overflow interrupt .1 timer a match/capture interrupt enable bit 0 disable interrupt 1 enable interrupt .0 not used for the s3c84bb/f84bb control registers s3c84bb/f84bb 4-42 tbcon ? timer b control register d0h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 timer b input clock selection bits 0 0 fxx 0 1 fxx/2 1 0 fxx/4 1 1 fxx/8 .5?.4 timer b interrupt time selection bits 0 0 elapsed time for low data value 0 1 elapsed time for high data value 1 0 elapsed time for low and high data values 1 1 invalid setting .3 timer b interrupt enable bit 0 disable interrupt 1 enable interrupt .2 timer b start/stop bit 0 stop timer b 1 start timer b .1 timer b mode selection bit 0 one-shot mode 1 repeating mode .0 timer b output flip-flop control bit 0 t-ff is low 1 t-ff is high note: fxx is selected clock for system. s3c84bb/f84bb control register 4-43 tccon0 ? timer c(0) control register f2h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 not used for the s3c84bb/f84bb (must keep always 0) .6-.4 timer c 3-bits prescaler bits 0 0 0 non devided 0 0 1 divided by 2 0 1 0 divided by 3 0 1 1 divided by 4 1 0 0 divided by 5 1 0 1 divided by 6 1 1 0 divided by 7 1 1 1 divided by 8 .3 timer c counter clear bit 0 no effect 1 clear the timer c(0) counter (auto-clear bit) .2 timer c mode selection bit 0 fxx/1 & pwm mode 1 fxx/64 & interval mode .1 timer c interrupt enable bit 0 disable interrupt 1 enable interrupt .0 timer c pending bit 0 no interrupt pending 0 clear pending bit when write 1 interrupt pending control registers s3c84bb/f84bb 4-44 tccon1 ? timer c(1) control register f3h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7 not used for the s3c84bb/f84bb (must keep always 0) .6-.4 timer c 3-bits prescaler bits 0 0 0 non devided 0 0 1 divided by 2 0 1 0 divided by 3 0 1 1 divided by 4 1 0 0 divided by 5 1 0 1 divided by 6 1 1 0 divided by 7 1 1 1 divided by 8 .3 timer c counter clear bit 0 no effect 1 clear the timer c(1) counter (auto-clear bit) .2 timer c mode selection bit 0 fxx/1 & pwm mode 1 fxx/64 & interval mode .1 timer c interrupt enable bit 0 disable interrupt 1 enable interrupt .0 timer c pending bit 0 no interrupt pending 0 clear pending bit when write 1 interrupt pending s3c84bb/f84bb control register 4-45 tintpnd ? timer a,1 interrupt pending register e9h set 1, bank 0 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value ? ? 0 0 0 0 0 0 read/write ? ? r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7-.6 not used for the s3c84bb/f84bb .5 timer 1(1) overflow interrupt pending bit 0 no interrupt pending 0 clear pending bit when write 1 interrupt pending .4 timer 1(1) match/capture interrupt pending bit 0 no interrupt pending 0 clear pending bit when write 1 interrupt pending .3 timer 1(0) overflow interrupt pending bit 0 no interrupt pending 0 clear pending bit when write 1 interrupt pending .2 timer 1(0) match/capture interrupt pending bit 0 no interrupt pending 0 clear pending bit when write 1 interrupt pending .1 timer a overflow interrupt pending bit 0 no interrupt pending 0 clear pending bit when write 1 interrupt pending .0 timer a match/capture interrupt pending bit 0 no interrupt pending 0 clear pending bit when write 1 interrupt pending control registers s3c84bb/f84bb 4-46 uartcon0 ? uart0 control register e3h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 operating mode and baud rate selection bits 0 0 mode 0: sio mode [fxx/(16 (brdata0 + 1))] 0 1 mode 1: 8-bit uart [fxx/(16 (brdata0 + 1))] 1 0 mode 2: 9-bit uart [fxx/16] 1 1 mode 3: 9-bit uart [fxx/(16 (brdata0 + 1))] .5 multiprocessor communication (1) enable bit (for modes 2 and 3 only) 0 disable 1 enable .4 serial data receive enable bit 0 disable 1 enable .3 location of the 9 th data bit to be transmitted in uart mode 2 or 3 ("0" or "1") .2 location of the 9 th data bit that was received in uart mode 2 or 3 ("0" or "1") .1 receive interrupt enable bit 0 disable receive interrupt 1 enable receive interrupt .0 transmit interrupt enable bit 0 disable transmit interrupt 1 enable transmit interrupt notes: 1. in mode 2 or 3, if the mce (uartcon.5) bit is set to "1", then the receive interrupt will not be activated if the received 9 th data bit is "0". in mode 1, if mce = "1?, then the receive interrupt will not be activated if a valid stop bit was not received. in mode 0, the mce(uartcon.5) bit should be "0". 2. the descriptions for 8-bit and 9-bit uart mode do not include start and stop bits for serial data receive and transmit. s3c84bb/f84bb control register 4-47 uartcon1 ? uart1 control register fbh set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value 0 0 0 0 0 0 0 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w addressing mode register addressing mode only .7?.6 operating mode and baud rate selection bits 0 0 mode 0: sio mode [fxx/(16 (brdata1 + 1))] 0 1 mode 1: 8-bit uart [fxx/(16 (brdata1 + 1))] 1 0 mode 2: 9-bit uart [fxx/16] 1 1 mode 3: 9-bit uart [fxx/(16 (brdata1 + 1))] .5 multiprocessor communication (1) enable bit (for modes 2 and 3 only) 0 disable 1 enable .4 serial data receive enable bit 0 disable 1 enable .3 location of the 9 th data bit to be transmitted in uart mode 2 or 3 ("0" or "1") .2 location of the 9 th data bit that was received in uart mode 2 or 3 ("0" or "1") .1 receive interrupt enable bit 0 disable receive interrupt 1 enable receive interrupt .0 transmit interrupt enable bit 0 disable transmit interrupt 1 enable transmit interrupt notes: 1. in mode 2 or 3, if the mce (uartcon.5) bit is set to "1", then the receive interrupt will not be activated if the received 9 th data bit is "0". in mode 1, if mce = "1?, then the receive interrupt will not be activated if a valid stop bit was not received. in mode 0, the mce(uartcon.5) bit should be "0". 2. the descriptions for 8-bit and 9-bit uart mode do not include start and stop bits for serial data receive and transmit. control registers s3c84bb/f84bb 4-48 uartpnd ? uart0,1 pending register e5h set 1, bank 1 bit identifier .7 .6 .5 .4 .3 .2 .1 .0 reset value ? ? ? ? 0 0 0 0 read/write ? ? ? ? r/w r/w r/w r/w addressing mode register addressing mode only .7?.4 not used for s3c84bb/f84bb .3 uart1 receive interrupt pending flag 0 not pending 0 clear pending bit (when write) 1 interrupt pending .2 uart1 transmit interrupt pending flag 0 not pending 0 clear pending bit (when write) 1 interrupt pending .1 uart0 receive interrupt pending flag 0 not pending 0 clear pending bit (when write) 1 interrupt pending .0 uart0 transmit interrupt pending flag 0 not pending 0 clear pending bit (when write) 1 interrupt pending notes: 1. in order to clear a data transmit or receive interrupt pending flag, you must write a "0" to the appropriate pending bit. 2. to avoid programming errors, we recommend using load instruction (except for ldb), when manipulating uartpnd values. s3c84bb/f84bb interrupt structure 5-1 interrupt structure overview the s3c8-series interrupt structure has three basic components: levels, vectors, and sources. the sam8 cpu recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. when a specific interrupt level has more than one vector address, the vector priorities are established in hardware. a vector address can be assigned to one or more sources. levels interrupt levels are the main unit for interrupt priority assignment and recognition. all peripherals and i/o blocks can issue interrupt requests. in other words, peripheral and i/o operations are interrupt-driven. there are eight possible interrupt levels: irq0?irq7, also called level 0?level 7. each interrupt level directly corresponds to an interrupt request number (irqn). the total number of interrupt levels used in the interrupt structure varies from device to device. the s3c84bb/f84bb interrupt structure recognizes eight interrupt levels. the interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. they are just identifiers for the interrupt levels that are recognized by the cpu. the relative priority of different interrupt levels is determined by settings in the interrupt priority register, ipr. interrupt group and subgroup logic controlled by ipr settings lets you define more complex priority relationships between different levels. vectors each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all. the maximum number of vectors that can be supported for a given level is 128 (the actual number of vectors used for s3c8-series devices is always much smaller). if an interrupt level has more than one vector address, the vector priorities are set in hardware. s3c84bb/f84bb uses twenty four vectors. sources a source is any peripheral that generates an interrupt. a source can be an external pin or a counter overflow. each vector can have several interrupt sources. in the s3c84bb/f84bb interrupt structure, there are twenty four possible interrupt sources. when a service routine starts, the respective pending bit should be either cleared automatically by hardware or cleared "manually" by program software. the characteristics of the source's pending mechanism determine which method would be used to clear its respective pending bit. interrupt structure s3c84bb/f84bb 5-2 interrupt types the three components of the s3c8 interrupt structure described before ? levels, vectors, and sources ? are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic. there are three possible combinations of interrupt structure components, called interrupt types 1, 2, and 3. the types differ in the number of vectors and interrupt sources assigned to each level (see figure 5-1): type 1: one level (irqn) + one vector (v 1 ) + one source (s 1 ) type 2: one level (irqn) + one vector (v 1 ) + multiple sources (s 1 ? s n ) type 3: one level (irqn) + multiple vectors (v 1 ? v n ) + multiple sources (s 1 ? s n , s n+1 ? s n+m ) in the s3c84bb/f84bb microcontroller, two interrupt types are implemented. vectors sources levels s1 v1 s2 type 2: irqn s3 sn v1 s1 v2 s2 type 3: irqn v3 s3 v1 s1 type 1: irqn vn sn + 1 sn sn + 2 sn + m notes: 1. the number of sn and vn value is expandable. 2. in the s3c84bb/f84bb implementation, interrupt types 1 and 3 are used. figure 5-1. s3c8-series interrupt types s3c84bb/f84bb interrupt structure 5-3 s3c84bb/f84bb interrupt structure the s3c84bb/f84bb microcontroller supports twenty four interrupt sources. all twenty four of the interrupt sources have a corresponding interrupt vector address. eight interrupt levels are recognized by the cpu in this device-specific interrupt structure, as shown in figure 5-2. when multiple interrupt levels are active, the interrupt priority register (ipr) determines the order in which contending interrupts are to be serviced. if multiple interrupts occur within the same interrupt level, the interrupt with the lowest vector address is usually processed first (the relative priorities of multiple interrupts within a single level are fixed in hardware). when the cpu grants an interrupt request, interrupt processing starts. all other interrupts are disabled and the program counter value and status flags are pushed to stack. the starting address of the service routine is fetched from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the service routine is executed. interrupt structure s3c84bb/f84bb 5-4 vectors sources levels reset(clear) notes: 1. w ithin a given interrupt level, the lower vector address has high priority. for example, b8h has higher priority than bah within the level irq0 the priorities within each level are set at the factory. 2. external interrupts are triggered by a rising or falling edge, depending on the corresponding control register setting. irq2 timer c(0) match/overflow timer c(1) match/overflow timer b underflow c8h irq1 h/w timer a match/capture irq0 timer a overflow h/w , s/w h/w , s/w h/w , s/w h/w , s/w bch beh b8h bah c0h c2h c4h c6h irq3 timer 1(0) match/capture timer 1(0) overflow timer 1(1) match/capture timer 1(1) overflow e0h e2h e4h e6h irq6 p4.0 external interrupt p4.1 external interrupt p4.2 external interrupt p4.3 external interrupt s/w s/w s/w s/w sio receive/transmit cah irq4 irq5 p8.4 external interrupt p8.5 external interrupt h/w , s/w h/w , s/w cch ceh f0h f2h f4h f6h irq7 uart0 data receive uart0 data transmit uart1 data receive uart1 data transmit s/w s/w s/w s/w e8h eah ech eeh p4.4 external interrupt p4.5 external interrupt p4.6 external interrupt p4.7 external interrupt s/w s/w s/w s/w h/w , s/w h/w , s/w s/w s/w s/w figure 5-2. s3c84bb/f84bb interrupt structure s3c84bb/f84bb interrupt structure 5-5 interrupt vector addresses all interrupt vector addresses for the s3c84bb/f84bb interrupt structure are stored in the vector address area of the internal 64-kbyte rom, 0h?ffffh (see figure 5-3). you can allocate unused locations in the vector address area as normal program memory. if you do so, please be careful not to overwrite any of the stored vector addresses (table 5-1 lists all vector addresses). the program reset address in the rom is 0100h. 65,535 0 (decimal) 255 00h 0100h ffh ffffh (hex) reset address interrupt vector area 64-kbyte memory area ~ ~ ~ ~ figure 5-3. rom vector address area interrupt structure s3c84bb/f84bb 5-6 table 5-1. interrupt vectors vector address request reset/clear decimal value hex value interrupt source interrupt level priority in level h/w s/w 256 100h basic timer(wdt) overflow resetb - 246 f6h uart1 transmit irq7 3 244 f4h uart1 receive 2 242 f2h uart0 transmit 1 240 f0h uart0 receive 0 238 eeh p4.7 external interrupt irq6 7 236 ech p4.6 external interrupt 6 234 eah p4.5 external interrupt 5 232 e8h p4.4 external interrupt 4 230 e6h p4.3 external interrupt 3 228 e4h p4.2 external interrupt 2 226 e2h p4.1 external interrupt 1 224 e0h p4.0 external interrupt 0 206 ceh p8.5 external interrupt irq5 1 204 cch p8.4 external interrupt 0 202 cah sio receive/transmit irq4 - 198 c6h timer 1(1) overflow irq3 3 196 c4h timer 1(1) match/capture 2 194 c2h timer 1(0) overflow 1 192 c0h timer 1(0) match/capture 0 190 beh timer c(1) match/overflow irq2 1 188 bch timer c(0) match/overflow 0 200 c8h timer b underflow irq1 - 186 bah timer a overflow irq0 1 184 b8h timer a match/capture 0 notes: 1. interrupt priorities are identified in inverse order: "0" is the highest priority, "1" is the next highest, and so on. 2. if two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority over one with a higher vector address. the priorities within a given level are fixed in hardware. s3c84bb/f84bb interrupt structure 5-7 enable/disable interrupt instructions (ei, di) executing the enable interrupts (ei) instruction globally enables the interrupt structure. all interrupts are then serviced as they occur according to the established priorities. note the system initialization routine executed after a reset must always contain an ei instruction to globally enable the interrupt structure. during the normal operation, you can execute the di (disable interrupt) instruction at any time to globally disable interrupt processing. the ei and di instructions change the value of bit 0 in the sym register. system-level interrupt control registers in addition to the control registers for specific interrupt sources, four system-level registers control interrupt processing: ? the interrupt mask register, imr, enables (un-masks) or disables (masks) interrupt levels. ? the interrupt priority register, ipr, controls the relative priorities of interrupt levels. ? the interrupt request register, irq, contains interrupt pending flags for each interrupt level (as opposed to each interrupt source). ? the system mode register, sym, enables or disables global interrupt processing (sym settings also enable fast interrupts and control the activity of external interface, if implemented). table 5-2. interrupt control register overview control register id r/w function description interrupt mask register imr r/w bit settings in the imr register enable or disable interrupt processing for each of the eight interrupt levels: irq0?irq7. interrupt priority register ipr r/w controls the relative processing priorities of the interrupt levels. the seven levels of s3c84bb/f84bb are organized into three groups: a, b, and c. group a is irq0 and irq1, group b is irq2, irq3 and irq4, and group c is irq5, irq6, and irq7. interrupt request register irq r this register contains a request pending bit for each interrupt level. system mode register sym r/w this register enables/disables fast interrupt processing, dynamic global interrupt processing, and external interface control (an external memory interface is not implemented in the s3c84bb/f84bb microcontroller). note: before imr register is changed to any value, all interrupts must be disable. using di instruction is recommended. interrupt structure s3c84bb/f84bb 5-8 interrupt processing control points interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. the system-level control points in the interrupt structure are: ? global interrupt enable and disable (by ei and di instructions or by direct manipulation of sym.0) ? interrupt level enable/disable settings (imr register) ? interrupt level priority settings (ipr register) ? interrupt source enable/disable settings in the corresponding peripheral control registers note when writing an application program that handles interrupt processing, be sure to include the necessary register file address (register pointer) information. interrupt request register (read-only) irq0-irq7, interrupts interrupt mask register polling cycle interrupt priority register global interrupt control (ei, di or sym.0 manipulation) s r q reset ei vector interrupt cycle figure 5-4. interrupt function diagram s3c84bb/f84bb interrupt structure 5-9 peripheral interrupt control registers for each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral (see table 5-3). table 5-3. interrupt source control and data registers interrupt source interrupt level register(s) location(s) in set 1 timer a overflow irq0 tintpnd e9h, bank 0 timer a match/capture tacon eah, bank 0 tadata ebh, bank 0 tacnt ech, bank 0 timer b underflow irq1 tbcon d0h, bank 0 tbdatah, tbdatal d1h, d2h, bank 0 timer c(0) match/overflow irq2 tccon0 f2h, bank 1 timer c(1) match/overflow tccon1 f3h, bank 1 tcdata0 f0h, bank 1 tcdata1 f1h, bank 1 timer1(0) match/capture irq3 t1datah0,t1datal0 e6h,e7h, bank 1 timer1(0) overflow t1datah1,t1datal1 e8h,e9h, bank 1 timer1(1)match/capture t1con0, t1con1 eah,ebh, bank1 timer1(1)overflow t1cnth0, t1cntl0 ech, edh, bank1 t1cnth1, t1cntl1 eeh, efh, bank1 sio receive/transmit irq4 siocon, siodata e1h,e0h, bank1 p8.5 external interrupt irq5 p8conh,p8conl edh,eeh, bank0 p8.4 external interrupt p8intpnd efh, bank0 p4.7 external interrupt irq6 p4conh f6h, bank 0 p4.6 external interrupt p4conl f7h, bank 0 p4.5 external interrupt p4int fah, bank 0 p4.4 external interrupt p4intpnd fbh, bank 0 p4.3 external interrupt p4.2 external interrupt p4.1 external interrupt p4.0 external interrupt uart0 receive/transmit irq7 uartcon0 e3h, bank 1 uart1 receive/transmit uartcon1 fbh, bank 1 udata0, udata1 e2h, fah, bank 1 uartpnd e5h, bank 1 interrupt structure s3c84bb/f84bb 5-10 system mode register (sym) the system mode register, sym (set 1, deh), is used to globally enable and disable interrupt processing (see figure 5-5). a reset clears sym.0 to "0". the instructions ei and di enable and disable global interrupt processing, respectively, by modifying the bit 0 value of the sym register. in order to enable interrupt processing an enable interrupt (ei) instruction must be included in the initialization routine, which follows a reset operation. although you can manipulate sym.0 directly to enable and disable interrupts during the normal operation, it is recommended to use the ei and di instructions for this purpose. system mode register (sym) deh, set 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb global interrupt enable bit: 0 = disable all interrupts processing 1 = enable all interrupts processing fast interrupt enable bit: 0 = disable fast interrupts processing 1 = enable fast interrupts processing fast interrupt level selection bits: 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 irq0 irq1 irq2 irq3 irq4 irq5 irq6 irq7 not used for the s3c84bb/f84bb figure 5-5. system mode register (sym) s3c84bb/f84bb interrupt structure 5-11 interrupt mask register (imr) the interrupt mask register, imr (set 1, ddh) is used to enable or disable interrupt processing for individual interrupt levels. after a reset, all imr bit values are undetermined and must therefore be written to their required settings by the initialization routine. each imr bit corresponds to a specific interrupt level: bit 1 to irq1, bit 2 to irq2, and so on. when the imr bit of an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). when you set a level's imr bit to "1", interrupt processing for the level is enabled (not masked). the imr register is mapped to register location ddh in set 1. bit values can be read and written by instructions using the register addressing mode. interrupt mask register (imr) ddh ,set 1, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 irq0 interrupt level # enable bit 0 = disable irq# interrupt 1 = enable irq# interrupt irq1 irq2 irq3 irq4 irq5 irq6 irq7 figure 5-6. interrupt mask register (imr) interrupt structure s3c84bb/f84bb 5-12 interrupt priority register (ipr) the interrupt priority register, ipr (set 1, bank 0, ffh), is used to set the relative priorities of the interrupt levels in the microcontroller?s interrupt structure. after a reset, all ipr bit values are undetermined and must therefore be written to their required settings by the initialization routine. when more than one interrupt sources are active, the source with the highest priority level is serviced first. if two sources belong to the same interrupt level, the source with the lower vector address usually has the priority (this priority is fixed in hardware). to support programming of the relative interrupt level priorities, they are organized into groups and subgroups by the interrupt logic. please note that these groups (and subgroups) are used only by ipr logic for the ipr register priority definitions (see figure 5-7): group a irq0, irq1 group b irq2, irq3, irq4 group c irq5, irq6, irq7 ipr group b irq2 b1 irq4 b2 irq3 b22 b21 ipr group a irq1 a2 irq0 a1 ipr group c c1 irq7 c2 irq6 c22 c21 irq5 figure 5-7. interrupt request priority groups as you can see in figure 5-8, ipr.7, ipr.4, and ipr.1 control the relative priority of interrupt groups a, b, and c. for example, the setting "001b" for these bits would select the group relationship b > c > a. the setting "101b" would select the relationship c > b > a. the functions of the other ipr bit settings are as follows: ? ipr.5 controls the relative priorities of group c interrupts. ? interrupt group c includes a subgroup that has an additional priority relationship among the interrupt levels 5, 6, and 7. ipr.6 defines the subgroup c relationship. ipr.5 controls the interrupt group c. ? ipr.0 controls the relative priority setting of irq0 and irq1 interrupts. s3c84bb/f84bb interrupt structure 5-13 group a 0 = irq0 > irq1 1 = irq1 > irq0 subgroup b 0 = irq3 > irq4 1 = irq4 > irq3 group c 0 = irq5 > (irq6, irq7) 1 = (irq6, irq7) > irq5 subgroup c 0 = irq6 > irq7 1 = irq7 > irq6 group b 0 = irq2 > (irq3, irq4) 1 = (irq3, irq4) > irq2 interrupt priority register (ipr) ffh ,set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 group priority: 0 0 0 = undefined 0 0 1 = b > c > a 0 1 0 = a > b >c 0 1 1 = b > a > c 1 0 0 = c > a > b 1 0 1 = c > b > a 1 1 0 = a > c > b 1 1 1 = undefined d7 d4 d1 figure 5-8. interrupt priority register (ipr) interrupt structure s3c84bb/f84bb 5-14 interrupt request register (irq) you can poll bit values in the interrupt request register, irq (set 1, dch), to monitor interrupt request status for all levels in the microcontroller?s interrupt structure. each bit corresponds to the interrupt level of the same number: bit 0 to irq0, bit 1 to irq1, and so on. a "0" indicates that no interrupt request is currently being issued for that level. a "1" indicates that an interrupt request has been generated for that level. irq bit values are read-only addressable using register addressing mode. you can read (test) the contents of the irq register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels. after a reset, all irq status bits are cleared to ?0?. you can poll irq register values even if a di instruction has been executed (that is, if global interrupt processing is disabled). if an interrupt occurs while the interrupt structure is disabled, the cpu will not service it. you can, however, still detect the interrupt request by polling the irq register. in this way, you can determine which events occurred while the interrupt structure was globally disabled. interrupt request register (irq) dch ,set 1, r lsb msb .7 .6 .5 .4 .3 .2 .1 .0 irq0 interrupt level # request pending bit 0 = irq# interrupt is not pending 1 = irq# interrupt is pending irq1 irq2 irq3 irq4 irq5 irq6 irq7 figure 5-9. interrupt request register (irq) s3c84bb/f84bb interrupt structure 5-15 interrupt pending function types overview there are two types of interrupt pending bits: one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other that must be cleared in the interrupt service routine. pending bits cleared automatically by hardware for interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding pending bit to "1" when a request occurs. it then issues an irq pulse to inform the cpu that an interrupt is waiting to be serviced. the cpu acknowledges the interrupt source by sending an iack, executes the service routine, and clears the pending bit to "0". this type of pending bit is not mapped and cannot, therefore, be read or written by application software. in the s3c84bb/f84bb interrupt structure, the timer b underflow interrupt (irq1) belongs to this category of interrupts in which pending condition is cleared automatically by hardware. pending bits cleared by the service routine the second type of pending bit is the one that should be cleared by program software. the service routine must clear the appropriate pending bit before a return-from-interrupt subroutine (iret) occurs. to do this, a "0" must be written to the corresponding pending bit location in the source?s mode or control register. in the s3c84bb/f84bb interrupt structure, pending conditions for irq4, irq5, irq6, and irq7 must be cleared in the interrupt service routine. interrupt structure s3c84bb/f84bb 5-16 interrupt source polling sequence the interrupt request polling and servicing sequence is as follows: 1. a source generates an interrupt request by setting the interrupt request bit to "1". 2. the cpu polling procedure identifies a pending condition for that source. 3. the cpu checks the source's interrupt level. 4. the cpu generates an interrupt acknowledge signal. 5. interrupt logic determines the interrupt's vector address. 6. the service routine starts and the source's pending bit is cleared to "0" (by hardware or by software). 7. the cpu continues polling for interrupt requests. interrupt service routines before an interrupt request is serviced, the following conditions must be met: ? interrupt processing must be globally enabled (ei, sym.0 = "1") ? the interrupt level must be enabled (imr register) ? the interrupt level must have the highest priority if more than one level is currently requesting service ? the interrupt must be enabled at the interrupt's source (peripheral control register) when all the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. the cpu then initiates an interrupt machine cycle that completes the following processing sequence: 1. reset (clear to "0") the interrupt enable bit in the sym register (sym.0) to disable all subsequent interrupts. 2. save the program counter (pc) and status flags to the system stack. 3. branch to the interrupt vector to fetch the address of the service routine. 4. pass control to the interrupt service routine. when the interrupt service routine is completed, the cpu issues an interrupt return (iret). the iret restores the pc and status flags, setting sym.0 to "1". it allows the cpu to process the next interrupt request. s3c84bb/f84bb interrupt structure 5-17 generating interrupt vector addresses the interrupt vector area in the rom (00h?ffh) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. vectored interrupt processing follows this sequence: 1. push the program counter's low-byte value to the stack. 2. push the program counter's high-byte value to the stack. 3. push the flag register values to the stack. 4. fetch the service routine's high-byte address from the vector location. 5. fetch the service routine's low-byte address from the vector location. 6. branch to the service routine specified by the concatenated 16-bit vector address. note a 16-bit vector address always begins at an even-numbered rom address within the range of 00h?ffh. nesting of vectored interrupts it is possible to nest a higher-priority interrupt request while a lower-priority request is being serviced. to do this, you must follow these steps: 1. push the current 8-bit interrupt mask register (imr) value to the stack (push imr). 2. load the imr register with a new mask value that enables only the higher priority interrupt. 3. execute an ei instruction to enable interrupt processing (a higher priority interrupt will be processed if it occurs). 4. when the lower-priority interrupt service routine ends, restore the imr to its original value by returning the previous mask value from the stack (pop imr). 5. execute an iret. depending on the application, you may be able to simplify the procedure above to some extent. interrupt structure s3c84bb/f84bb 5-18 notes s3c84bb/f84bb instruction set 6-1 instruction set overview the instruction set is specifically designed to support large register files that are typical of most s3c8-series microcontrollers. there are 78 instructions. the powerful data manipulation capabilities and features of the instruction set include: ? a full complement of 8-bit arithmetic and logic operations, including multiply and divide ? no special i/o instructions (i/o control/data registers are mapped directly into the register file) ? decimal adjustment included in binary-coded decimal (bcd) operations ? 16-bit (word) data can be incremented and decremented ? flexible instructions for bit addressing, rotate, and shift operations data types the cpu performs operations on bits, bytes, bcd digits, and two-byte words. bits in the register file can be set, cleared, complemented, and tested. bits within a byte are numbered from 7 to 0, where bit 0 is the least significant (right-most) bit. register addressing to access an individual register, an 8-bit address in the range 0?255 or the 4-bit address of a working register is specified. paired registers can be used to construct 16-bit data, 16-bit program memory or data memory addresses. for detailed information about register addressing, please refer to chapter 2, "address spaces." addressing modes there are seven explicit addressing modes: register (r), indirect register (ir), indexed (x), direct (da), relative (ra), immediate (im), and indirect (ia). for detailed descriptions of these addressing modes, please refer to chapter 3, "addressing modes." instruction set s3c84bb/f84bb 6-2 table 6-1. instruction group summary mnemonic operands instruction load instructions clr dst clear ld dst,src load ldb dst,src load bit lde dst,src load external data memory ldc dst,src load program memory lded dst,src load external data memory and decrement ldcd dst,src load program memory and decrement ldei dst,src load external data memory and increment ldci dst,src load program memory and increment ldepd dst,src load external data memory with pre-decrement ldcpd dst,src load program memory with pre-decrement ldepi dst,src load external data memory with pre-increment ldcpi dst,src load program memory with pre-increment ldw dst,src load word pop dst pop from stack popud dst,src pop user stack (decrementing) popui dst,src pop user stack (incrementing) push src push to stack pushud dst,src push user stack (decrementing) pushui dst,src push user stack (incrementing) note: lde, lded, ldei, ldepp, and ldepi instructions can be used to read/write the data from the 64-kbyte data memory. s3c84bb/f84bb instruction set 6-3 table 6-1. instruction group summary (continued) mnemonic operands instruction arithmetic instructions adc dst,src add with carry add dst,src add cp dst,src compare da dst decimal adjust dec dst decrement decw dst decrement word div dst,src divide inc dst increment incw dst increment word mult dst,src multiply sbc dst,src subtract with carry sub dst,src subtract logic instructions and dst,src logical and com dst complement or dst,src logical or xor dst,src logical exclusive or instruction set s3c84bb/f84bb 6-4 table 6-1. instruction group summary (continued) mnemonic operands instruction program control instructions btjrf dst,src bit test and jump relative on false btjrt dst,src bit test and jump relative on true call dst call procedure cpije dst,src compare, increment and jump on equal cpijne dst,src compare, increment and jump on non-equal djnz r,dst decrement register and jump on non-zero enter enter exit exit iret interrupt return jp cc,dst jump on condition code jp dst jump unconditional jr cc,dst jump relative on condition code next next ret return wfi wait for interrupt bit manipulation instructions band dst,src bit and bcp dst,src bit compare bitc dst bit complement bitr dst bit reset bits dst bit set bor dst,src bit or bxor dst,src bit xor tcm dst,src test complement under mask tm dst,src test under mask s3c84bb/f84bb instruction set 6-5 table 6-1. instruction group summary (concluded) mnemonic operands instruction rotate and shift instructions rl dst rotate left rlc dst rotate left through carry rr dst rotate right rrc dst rotate right through carry sra dst shift right arithmetic swap dst swap nibbles cpu control instructions ccf complement carry flag di disable interrupts ei enable interrupts idle enter idle mode nop no operation rcf reset carry flag sb0 set bank 0 sb1 set bank 1 scf set carry flag srp src set register pointers srp0 src set register pointer 0 srp1 src set register pointer 1 stop enter stop mode instruction set s3c84bb/f84bb 6-6 flags register (flags) the flags register flags contains eight bits which describe the current status of cpu operations. four of these bits, flags.7?flags.4, can be tested and used with conditional jump instructions. two other flag bits, flags.3 and flags.2, are used for bcd arithmetic. the flags register also contains a bit to indicate the status of fast interrupt processing (flags.1) and a bank address status bit (flags.0) to indicate whether register bank 0 or bank 1 is currently being addressed. flags register can be set or reset by instructions as long as its outcome does not affect the flags, such as, load instruction. logical and arithmetic instructions such as, and, or, xor, add, and sub can affect the flags register. for example, the and instruction updates the zero, sign and overflow flags based on the outcome of the and instruction. if the and instruction uses the flags register as the destination, then two write will simultaneously occur to the flags register producing an unpredictable result. system flags register (flags) d5h ,set 1, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 bank address status flag (ba) fast interrupt status flag (fs) half-carry flag (h) decimal adjust flag (d) carry flag (c) zero flag (z) sign flag (s) overflow flag (v) figure 6-1. system flags register (flags) s3c84bb/f84bb instruction set 6-7 flag descriptions c carry flag (flags.7) the c flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (msb). after rotate and shift operations have been performed, it contains the last value shifted out of the specified register. program instructions can set, clear, or complement the carry flag. z zero flag (flags.6) for arithmetic and logic operations, the z flag is set to "1" if the result of the operation is zero. in operations that test register bits, and in shift and rotate operations, the z flag is set to "1" if the result is logic zero. s sign flag (flags.5) following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the msb of the result. a logic zero indicates a positive number and a logic one indicates a negative number. v overflow flag (flags.4) the v flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than ? 128. it is cleared to "0" after a logic operation has been performed. d decimal adjust flag (flags.3) the da bit is used to specify what type of instruction was executed last during bcd operations so that a subsequent decimal adjust operation can execute correctly. the da bit is not usually accessed by programmers, and it cannot be addressed as a test condition. h half-carry flag (flags.2 ) the h bit is set to "1" whenever an addition generates a carry-out of bit 3, or when a subtraction borrows out of bit 4. it is used by the decimal adjust (da) instruction to convert the binary result of a previous addition or subtraction into the correct decimal (bcd) result. the h flag is normally not accessed directly by a program. fis fast interrupt status flag (flags.1) the fis bit is set during a fast interrupt cycle and reset during the iret following interrupt servicing. when set, it inhibits all interrupts and causes the fast interrupt return to be executed when the iret instruction is executed. ba bank address flag (flags.0) the ba flag indicates which register bank in the set 1 area of the internal register file is currently selected, bank 0 or bank 1. the ba flag is cleared to "0" (select bank 0) when the sb0 instruction is executed and is set to "1" (select bank 1) when the sb1 instruction is executed. instruction set s3c84bb/f84bb 6-8 instruction set notation table 6-2. flag notation conventions flag description c carry flag z zero flag s sign flag v overflow flag d decimal-adjust flag h half-carry flag 0 cleared to logic zero 1 set to logic one * set or cleared according to operation ? value is unaffected x value is undefined table 6-3. instruction set symbols symbol description dst destination operand src source operand @ indirect register address prefix pc program counter ip instruction pointer flags flags register (d5h) rp register pointer # immediate operand or register address prefix h hexadecimal number suffix d decimal number suffix b binary number suffix opc opcode s3c84bb/f84bb instruction set 6-9 table 6-4. instruction notation conventions notation description actual operand range cc condition code see list of condition codes in table 6-6. r working register only rn (n = 0?15) rb bit (b) of working register rn.b (n = 0?15, b = 0?7) r0 bit 0 (lsb) of working register rn (n = 0?15) rr working register pair rrp (p = 0, 2, 4, ..., 14) r register or working register reg or rn (reg = 0?255, n = 0?15) rb bit "b" of register or working register reg.b (reg = 0?255, b = 0?7) rr register pair or working register pair reg or rrp (reg = 0?254, even number only, where p = 0, 2, ..., 14) ia indirect addressing mode addr (addr = 0?254, even number only) ir indirect working register only @rn (n = 0?15) ir indirect register or indirect working register @rn or @reg (reg = 0?255, n = 0?15) irr indirect working register pair only @rrp (p = 0, 2, ..., 14) irr indirect register pair or indirect working register pair @rrp or @reg (reg = 0?254, even only, where p = 0, 2, ..., 14) x indexed addressing mode #reg[rn] (reg = 0?255, n = 0?15) xs indexed (short offset) addressing mode #addr[rrp] (addr = range ?128 to +127, where p = 0, 2, ..., 14) xl indexed (long offset) addressing mode #addr [rrp] (addr = range 0?65535, where p = 2, ..., 14) da direct addressing mode addr (addr = range 0?65535) ra relative addressing mode addr (addr = a number from +127 to ?128 that is an offset relative to the address of the next instruction) im immediate addressing mode #data (data = 0?255) iml immediate (long) addressing mode #data (data = 0?65535) instruction set s3c84bb/f84bb 6-10 table 6-5. opcode quick reference opcode map lower nibble (hex) ? 0 1 2 3 4 5 6 7 u 0 dec r1 dec ir1 add r1,r2 add r1,ir2 add r2,r1 add ir2,r1 add r1,im bor r0?rb p 1 rlc r1 rlc ir1 adc r1,r2 adc r1,ir2 adc r2,r1 adc ir2,r1 adc r1,im bcp r1.b, r2 p 2 inc r1 inc ir1 sub r1,r2 sub r1,ir2 sub r2,r1 sub ir2,r1 sub r1,im bxor r0?rb e 3 jp irr1 srp/0/1 im sbc r1,r2 sbc r1,ir2 sbc r2,r1 sbc ir2,r1 sbc r1,im btjr r2.b, ra r 4 da r1 da ir1 or r1,r2 or r1,ir2 or r2,r1 or ir2,r1 or r1,im ldb r0?rb 5 pop r1 pop ir1 and r1,r2 and r1,ir2 and r2,r1 and ir2,r1 and r1,im bitc r1.b n 6 com r1 com ir1 tcm r1,r2 tcm r1,ir2 tcm r2,r1 tcm ir2,r1 tcm r1,im band r0?rb i 7 push r2 push ir2 tm r1,r2 tm r1,ir2 tm r2,r1 tm ir2,r1 tm r1,im bit r1.b b 8 decw rr1 decw ir1 pushud ir1,r2 pushui ir1,r2 mult r2,rr1 mult ir2,rr1 mult im,rr1 ld r1, x, r2 b 9 rl r1 rl ir1 popud ir2,r1 popui ir2,r1 div r2,rr1 div ir2,rr1 div im,rr1 ld r2, x, r1 l a incw rr1 incw ir1 cp r1,r2 cp r1,ir2 cp r2,r1 cp ir2,r1 cp r1,im ldc r1, irr2, xl e b clr r1 clr ir1 xor r1,r2 xor r1,ir2 xor r2,r1 xor ir2,r1 xor r1,im ldc r2, irr2, xl c rrc r1 rrc ir1 cpije ir,r2,ra ldc r1,irr2 ldw rr2,rr1 ldw ir2,rr1 ldw rr1,iml ld r1, ir2 h d sra r1 sra ir1 cpijne irr,r2,ra ldc r2,irr1 call ia1 ld ir1,im ld ir1, r2 e e rr r1 rr ir1 ldcd r1,irr2 ldci r1,irr2 ld r2,r1 ld r2,ir1 ld r1,im ldc r1, irr2, xs x f swap r1 swap ir1 ldcpd r2,irr1 ldcpi r2,irr1 call irr1 ld ir2,r1 call da1 ldc r2, irr1, xs s3c84bb/f84bb instruction set 6-11 table 6-5. opcode quick reference (continued) opcode map lower nibble (hex) ? 8 9 a b c d e f u 0 ld r1,r2 ld r2,r1 djnz r1,ra jr cc,ra ld r1,im jp cc,da inc r1 next p 1 enter p 2 exit e 3 wfi r 4 sb0 5 sb1 n 6 idle i 7 stop b 8 di b 9 ei l a ret e b iret c rcf h d scf e e ccf x f ld r1,r2 ld r2,r1 djnz r1,ra jr cc,ra ld r1,im jp cc,da inc r1 nop instruction set s3c84bb/f84bb 6-12 condition codes the opcode of a conditional jump always contains a 4-bit field called the condition code (cc). this specifies under which conditions it is to execute the jump. for example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. condition codes are listed in table 6-6. the carry (c), zero (z), sign (s), and overflow (v) flags are used to control the operation of conditional jump instructions. table 6-6. condition codes binary mnemonic description flags set 0000 f always false ? 1000 t always true ? 0111 (1) c carry c = 1 1111 (1) nc no carry c = 0 0110 (1) z zero z = 1 1110 (1) nz not zero z = 0 1101 pl plus s = 0 0101 mi minus s = 1 0100 ov overflow v = 1 1100 nov no overflow v = 0 0110 (1) eq equal z = 1 1110 (1) ne not equal z = 0 1001 ge greater than or equal (s xor v) = 0 0001 lt less than (s xor v) = 1 1010 gt greater than (z or (s xor v)) = 0 0010 le less than or equal (z or (s xor v)) = 1 1111 (1) uge unsigned greater than or equal c = 0 0111 (1) ult unsigned less than c = 1 1011 ugt unsigned greater than (c = 0 and z = 0) = 1 0011 ule unsigned less than or equal (c or z) = 1 notes: 1. it indicate condition codes which are related to two different mnemonics but which test the same flag. for example, z and eq are both true if the zero flag (z) is set, but after an add instruction, z would probably be used. following a cp instruction, you would probably want to use the instruction eq. 2. for operations using unsigned numbers, the special condition codes uge, ult, ugt, and ule must be used. s3c84bb/f84bb instruction set 6-13 instruction descriptions this chapter contains detailed information and programming examples for each instruction in the s3c8-series instruction set. information is arranged in a consistent format for improved readability and for quick reference. the following information is included in each instruction description: ? instruction name (mnemonic) ? full instruction name ? source/destination format of the instruction operand ? shorthand notation of the instruction's operation ? textual description of the instruction's effect ? flag settings that may be affected by the instruction ? detailed description of the instruction's format, execution time, and addressing mode(s) ? programming example(s) explaining how to use the instruction instruction set s3c84bb/f84bb 6-14 adc ? add with carry adc dst,src operation: dst dst + src + c the source operand, along with the carry flag setting, is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. two's-complement addition is performed. in multiple-precision arithmetic, this instruction lets the carry value from the addition of low-order operands be carried into the addition of high-order operands. flags: c: set if there is a carry from the most significant bit of the result; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. d: always cleared to "0". h: set if there is a carry from the most significant bit of the low-order four bits of the result; cleared otherwise. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 12 r r 6 13 r lr opc src dst 3 6 14 r r 15 r ir opc dst src 3 6 16 r im examples: given: r1 = 10h, r2 = 03h, c flag = "1", register 01h = 20h, register 02h = 03h, and register 03h = 0ah: adc r1,r2 r1 = 14h, r2 = 03h adc r1,@r2 r1 = 1bh, r2 = 03h adc 01h,02h register 01h = 24h, register 02h = 03h adc 01h,@02h register 01h = 2bh, register 02h = 03h adc 01h,#11h register 01h = 32h in the first example, the destination register r1 contains the value 10h, the carry flag is set to "1" and the source working register r2 contains the value 03h. the statement "adc r1,r2" adds 03h and the carry flag value ("1") to the destination value 10h, leaving 14h in the register r1. s3c84bb/f84bb instruction set 6-15 add ? add add dst,src operation: dst dst + src the source operand is added to the destination operand and the sum is stored in the destination. the contents of the source are unaffected. two's-complement addition is performed. flags: c: set if there is a carry from the most significant bit of the result; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. d: always cleared to "0". h: set if a carry from the low-order nibble occurred. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 02 r r 6 03 r lr opc src dst 3 6 04 r r 05 r ir opc dst src 3 6 06 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: add r1,r2 r1 = 15h, r2 = 03h add r1,@r2 r1 = 1ch, r2 = 03h add 01h,02h register 01h = 24h, register 02h = 03h add 01h,@02h register 01h = 2bh, register 02h = 03h add 01h,#25h register 01h = 46h in the first example, the destination working register r1 contains 12h and the source working register r2 contains 03h. the statement "add r1,r2" adds 03h to 12h, leaving the value 15h in the register r1. instruction set s3c84bb/f84bb 6-16 and ? logical and and dst,src operation: dst dst and src the source operand is logically anded with the destination operand. the result is stored in the destination. the and operation causes a "1" bit to be stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. the contents of the source are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 52 r r 6 53 r lr opc src dst 3 6 54 r r 55 r ir opc dst src 3 6 56 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: and r1,r2 r1 = 02h, r2 = 03h and r1,@r2 r1 = 02h, r2 = 03h and 01h,02h register 01h = 01h, register 02h = 03h and 01h,@02h register 01h = 00h, register 02h = 03h and 01h,#25h register 01h = 21h in the first example, the destination working register r1 contains the value 12h and the source working register r2 contains 03h. the statement "and r1,r2" logically ands the source operand 03h with the destination operand value 12h, leaving the value 02h in the register r1. s3c84bb/f84bb instruction set 6-17 band ? bit and band dst,src.b band dst.b,src operation: dst(0) dst(0) and src(b) or dst(b) dst(b) and src(0) the specified bit of the source (or the destination) is logically anded with the zero bit (lsb) of the destination (or the source). the resultant bit is stored in the specified bit of the destination. no other bits of the destination are affected. the source is unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 67 r0 rb opc src | b | 1 dst 3 6 67 rb r0 note: in the second byte of the 3-byte instruction formats, the destination (or the source) address is four bits, the bit address "b" is three bits, and the lsb address value is one bit in length. examples: given: r1 = 07h and register 01h = 05h: band r1,01h.1 r1 = 06h, register 01h = 05h band 01h.1,r1 register 01h = 05h, r1 = 07h in the first example, the source register 01h contains the value 05h (00000101b) and the destination working register r1 contains 07h (00000111b). the statement "band r1,01h.1" ands the bit 1 value of the source register ("0") with the bit 0 value of the register r1 (destination), leaving the value 06h (00000110b) in the register r1. instruction set s3c84bb/f84bb 6-18 bcp ? bit compare bcp dst,src.b operation: dst(0) ? src(b) the specified bit of the source is compared to (subtracted from) bit zero (lsb) of the destination. the zero flag is set if the bits are the same; otherwise it is cleared. the contents of both operands are unaffected by the comparison. flags: c: unaffected. z: set if the two bits are the same; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 17 r0 rb note : in the second byte of the instruction format, the destination address is four bits, the bit address "0" is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h and register 01h = 01h: bcp r1,01h.1 r1 = 07h, register 01h = 01h if the destination working register r1 contains the value 07h (00000111b) and the source register 01h contains the value 01h (00000001b), the statement "bcp r1,01h.1" compares bit one of the source register (01h) and bit zero of the destination register (r1). because the bit values are not identical, the zero flag bit (z) is cleared in the flags register (0d5h). s3c84bb/f84bb instruction set 6-19 bitc ? bit complement bitc dst.b operation: dst(b) not dst(b) this instruction complements the specified bit within the destination without affecting any other bit in the destination. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst | b | 0 2 4 57 rb note : in the second byte of the instruction format, the destination address is four bits, the bit address ?b? is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h bitc r1.1 r1 = 05h if the working register r1 contains the value 07h (00000111b), the statement "bitc r1.1" complements bit one of the destination and leaves the value 05h (00000101b) in the register r1. because the result of the complement is not "0", the zero flag (z) in the flags register (0d5h) is cleared. instruction set s3c84bb/f84bb 6-20 bitr ? bit reset bitr dst.b operation: dst(b) 0 the bitr instruction clears the specified bit within the destination without affecting any other bit in the destination. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst | b | 0 2 4 77 rb note : in the second byte of the instruction format, the destination address is four bits, the bit address ?0? is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h: bitr r1.1 r1 = 05h if the value of the working register r1 is 07h (00000111b), the statement "bitr r1.1" clears bit one of the destination register r1, leaving the value 05h (00000101b). s3c84bb/f84bb instruction set 6-21 bits ? bit set bits dst.b operation: dst(b) 1 the bits instruction sets the specified bit within the destination without affecting any other bit in the destination. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst | b | 1 2 4 77 rb note: in the second byte of the instruction format, the destination address is four bits, the bit address ?b? is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h: bits r1.3 r1 = 0fh if the working register r1 contains the value 07h (00000111b), the statement "bits r1.3" sets bit three of the destination register r1 to "1", leaving the value 0fh (00001111b). instruction set s3c84bb/f84bb 6-22 bor ? bit or bor dst,src.b bor dst.b,src operation: dst(0) dst(0) or src(b) or dst(b) dst(b) or src(0) the specified bit of the source (or the destination) is logically ored with bit zero (lsb) of the destination (or the source). the resulting bit value is stored in the specified bit of the destination. no other bits of the destination are affected. the source is unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 07 r0 rb opc src | b | 1 dst 3 6 07 rb r0 note : in the second byte of the 3-byte instruction format, the destination (or the source) address is four bits, the bit address ?b? is three bits, and the lsb address value is one bit. examples: given: r1 = 07h and register 01h = 03h: bor r1, 01h.1 r1 = 07h, register 01h = 03h bor 01h.2, r1 register 01h = 07h, r1 = 07h in the first example, the destination working register r1 contains the value 07h (00000111b) and the source register 01h the value 03h (00000011b). the statement "bor r1,01h.1" logically ors bit one of the register 01h (source) with bit zero of r1 (destination). this leaves the same value (07h) in the working register r1. in the second example, the destination register 01h contains the value 03h (00000011b) and the source working register r1 the value 07h (00000111b). the statement "bor 01h.2,r1" logically ors bit two of the register 01h (destination) with bit zero of r1 (source). this leaves the value 07h in the register 01h. s3c84bb/f84bb instruction set 6-23 btjrf ? bit test, jump relative on false btjrf dst,src.b operation: if src(b) is a "0", then pc pc + dst the specified bit within the source operand is tested. if it is a "0", the relative address is added to the program counter and control passes to the statement whose address is currently in the program counter. otherwise, the instruction following the btjrf instruction is executed. flags: no flags are affected. format: (note) bytes cycles opcode (hex) addr mode dst src opc src | b | 0 dst 3 10 37 ra rb note: in the second byte of the instruction format, the source address is four bits, the bit address "b" is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h: btjrf skip,r1.3 pc jumps to skip location if the working register r1 contains the value 07h (00000111b), the statement "btjrf skip,r1.3" tests bit 3. because it is "0", the relative address is added to the pc and the pc jumps to the memory location pointed to by the skip (remember that the memory location must be within the allowed range of + 127 to ? 128). instruction set s3c84bb/f84bb 6-24 btjrt ? bit test, jump relative on true btjrt dst,src.b operation: if src(b) is a "1", then pc pc + dst the specified bit within the source operand is tested. if it is a "1", the relative address is added to the program counter and control passes to the statement whose address is now in the pc. otherwise, the instruction following the btjrt instruction is executed. flags: no flags are affected. format: (note) bytes cycles opcode (hex) addr mode dst src opc src | b | 1 dst 3 10 37 ra rb note: in the second byte of the instruction format, the source address is four bits, the bit address "b" is three bits, and the lsb address value is one bit in length. example: given: r1 = 07h: btjrt skip,r1.1 if the working register r1 contains the value 07h (00000111b), the statement "btjrt skip,r1.1" tests bit one in the source register (r1). because it is a "1", the relative address is added to the pc and the pc jumps to the memory location pointed to by the skip. remember that the memory location addressed by the btjrt instruction must be within the allowed range of + 127 to ? 128. s3c84bb/f84bb instruction set 6-25 bxor ? bit xor bxor dst,src.b bxor dst.b,src operation: dst(0) dst(0) xor src(b) or dst(b) dst(b) xor src(0) the specified bit of the source (or the destination) is logically exclusive-ored with bit zero (lsb) of the destination (or the source). the result bit is stored in the specified bit of the destination. no other bits of the destination are affected. the source is unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: cleared to "0". v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 27 r0 rb opc src | b | 1 dst 3 6 27 rb r0 note : in the second byte of the 3-byte instruction format, the destination (or the source) address is four bits, the bit address "b" is three bits, and the lsb address value is one bit in length. examples: given: r1 = 07h (00000111b) and register 01h = 03h (00000011b): bxor r1,01h.1 r1 = 06h, register 01h = 03h bxor 01h.2,r1 register 01h = 07h, r1 = 07h in the first example, the destination working register r1 has the value 07h (00000111b) and the source register 01h has the value 03h (00000011b). the statement "bxor r1,01h.1" exclusive- ors bit one of the register 01h (the source) with bit zero of r1 (the destination). the result bit value is stored in bit zero of r1, changing its value from 07h to 06h. the value of the source register 01h is unaffected. instruction set s3c84bb/f84bb 6-26 call ? call procedure call dst operation: sp sp?1 @sp pcl sp sp?1 @sp pch pc dst the contents of the program counter are pushed onto the top of the stack. the program counter value used is the address of the first instruction following the call instruction. the specified destination address is then loaded into the program counter and points to the first instruction of a procedure. at the end of the procedure the return instruction (ret) can be used to return to the original program flow. ret pops the top of the stack back into the program counter. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst 3 14 f6 da opc dst 2 12 f4 irr opc dst 2 14 d4 ia examples: given: r0 = 35h, r1 = 21h, pc = 1a47h, and sp = 0002h: call 3521h sp = 0000h (memory locations 0000h = 1ah, 0001h = 4ah, where, 4ah is the address that follows the instruction.) call @rr0 sp = 0000h (0000h = 1ah, 0001h = 49h) call #40h sp = 0000h (0000h = 1ah, 0001h = 49h) in the first example, if the program counter value is 1a47h and the stack pointer contains the value 0002h, the statement "call 3521h" pushes the current pc value onto the top of the stack. the stack pointer now points to the memory location 0000h. the pc is then loaded with the value 3521h, the address of the first instruction in the program sequence to be executed. if the contents of the program counter and the stack pointer are the same as in the first example, the statement "call @rr0" produces the same result except that the 49h is stored in stack location 0001h (because the two-byte instruction format was used). the pc is then loaded with the value 3521h, the address of the first instruction in the program sequence to be executed. assuming that the contents of the program counter and the stack pointer are the same as in the first example, if the program address 0040h contains 35h and the program address 0041h contains 21h, the statement "call #40h" produces the same result as in the second example. s3c84bb/f84bb instruction set 6-27 ccf ? complement carry flag ccf operation: c not c the carry flag (c) is complemented. if c = "1", the value of the carry flag is changed to logic zero. if c = "0", the value of the carry flag is changed to logic one. flags: c: complemented. no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 ef example: given: the carry flag = "0": ccf if the carry flag = "0", the ccf instruction complements it in the flags register (0d5h), changing its value from logic zero to logic one. instruction set s3c84bb/f84bb 6-28 clr ? clear clr dst operation: dst "0" the destination location is cleared to "0". flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 b0 r 4 b1 ir examples: given: register 00h = 4fh, register 01h = 02h, and register 02h = 5eh: clr 00h register 00h = 00h clr @01h register 01h = 02h, register 02h = 00h in register (r) addressing mode, the statement "clr 00h" clears the destination register 00h value to 00h. in the second example, the statement "clr @01h" uses indirect register (ir) addressing mode to clear the 02h register value to 00h. s3c84bb/f84bb instruction set 6-29 com ? complement com dst operation: dst not dst the contents of the destination location are complemented (one's complement). all "1s" are changed to "0s", and vice-versa. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 60 r 4 61 ir examples: given: r1 = 07h and register 07h = 0f1h: com r1 r1 = 0f8h com @r1 r1 = 07h, register 07h = 0eh in the first example, the destination working register r1 contains the value 07h (00000111b). the statement "com r1" complements all the bits in r1: all logic ones are changed to logic zeros, and logic zeros to logic ones, leaving the value 0f8h (11111000b). in the second example, indirect register (ir) addressing mode is used to complement the value of the destination register 07h (11110001b), leaving the new value 0eh (00001110b). instruction set s3c84bb/f84bb 6-30 cp ? compare cp dst,src operation: dst?src the source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. the contents of both operands are unaffected by the comparison. flags: c: set if a "borrow" occurred (src > dst); cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 a2 r r 6 a3 r lr opc src dst 3 6 a4 r r 6 a5 r ir opc dst src 3 6 a6 r im examples: 1. given: r1 = 02h and r2 = 03h: cp r1,r2 set the c and s flags the destination working register r1 contains the value 02h and the source register r2 contains the value 03h. the statement "cp r1,r2" subtracts the r2 value (source/subtrahend) from the r1 value (destination/minuend). because a "borrow" occurs and the difference is negative, the c and the s flag values are "1". 2. given: r1 = 05h and r2 = 0ah: cp r1,r2 jp uge,skip inc r1 skip ld r3,r1 in this example, the destination working register r1 contains the value 05h which is less than the contents of the source working register r2 (0ah). the statement "cp r1,r2" generates c = "1" and the jp instruction does not jump to the skip location. after the statement "ld r3,r1" executes, the value 06h remains in the working register r3. s3c84bb/f84bb instruction set 6-31 cpije ? compare, increment, and jump on equal cpije dst,src,ra operation: if dst?src = "0", pc pc + ra ir ir + 1 the source operand is compared to (subtracted from) the destination operand. if the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter. otherwise, the instruction immediately following the cpije instruction is executed. in either case, the source pointer is incremented by one before the next instruction is executed. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst ra 3 12 c2 r ir example: given: r1 = 02h, r2 = 03h, and register 03h = 02h: cpije r1,@r2,skip r2 = 04h, pc jumps to skip location in this example, the working register r1 contains the value 02h, the working register r2 the value 03h, and the register 03 contains 02h. the statement "cpije r1,@r2,skip" compares the @r2 value 02h (00000010b) to 02h (00000010b). because the result of the comparison is equal , the relative address is added to the pc and the pc then jumps to the memory location pointed to by skip. the source register (r2) is incremented by one, leaving a value of 04h. remember that the memory location addressed by the cpije instruction must be within the allowed range of + 127 to ? 128. instruction set s3c84bb/f84bb 6-32 cpijne ? compare, increment, and jump on non-equal cpijne dst,src,ra operation: if dst?src "0", pc pc + ra ir ir + 1 the source operand is compared to (subtracted from) the destination operand. if the result is not "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter. otherwise the instruction following the cpijne instruction is executed. in either case the source pointer is incremented by one before the next instruction. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst ra 3 12 d2 r ir example: given: r1 = 02h, r2 = 03h, and register 03h = 04h: cpijne r1,@r2,skip r2 = 04h, pc jumps to skip location the working register r1 contains the value 02h, the working register r2 (the source pointer) the value 03h, and the general register 03 the value 04h. the statement "cpijne r1,@r2,skip" subtracts 04h (00000100b) from 02h (00000010b). because the result of the comparison is non- equal , the relative address is added to the pc and the pc then jumps to the memory location pointed to by skip. the source pointer register (r2) is also incremented by one, leaving a value of 04h. remember that the memory location addressed by the cpijne instruction must be within the allowed range of + 127 to ? 128. s3c84bb/f84bb instruction set 6-33 da ? decimal adjust da dst operation: dst da dst the destination operand is adjusted to form two 4-bit bcd digits following an addition or subtraction operation. for addition (add, adc) or subtraction (sub, sbc), the following table indicates the operation performed (the operation is undefined if the destination operand is not the result of a valid addition or subtraction of bcd digits): instruction carry before da bits 4?7 value (hex) h flag before da bits 0?3 value (hex) number added to byte carry after da 0 0?9 0 0?9 00 0 0 0?8 0 a?f 06 0 0 0?9 1 0?3 06 0 add 0 a?f 0 0?9 60 1 adc 0 9?f 0 a?f 66 1 0 a?f 1 0?3 66 1 1 0?2 0 0?9 60 1 1 0?2 0 a?f 66 1 1 0?3 1 0?3 66 1 0 0?9 0 0?9 00 = ? 00 0 sub 0 0?8 1 6?f fa = ? 06 0 sbc 1 7?f 0 0?9 a0 = ? 60 1 1 6?f 1 6?f 9a = ? 66 1 flags: c: set if there was a carry from the most significant bit; cleared otherwise (see table). z: set if result is "0"; cleared otherwise. s: set if result bit 7 is set; cleared otherwise. v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 40 r 4 41 ir instruction set s3c84bb/f84bb 6-34 da ? decimal adjust da (continued) example: given: the working register r0 contains the value 15 (bcd), the working register r1 contains 27 (bcd), and the address 27h contains 46 (bcd): add r1,r0 ; c "0", h "0", bits 4?7 = 3, bits 0?3 = c, r1 3ch da r1 ; r1 3ch + 06 if an addition is performed using the bcd values 15 and 27, the result should be 42. the sum is incorrect, however, when the binary representations are added in the destination location using the standard binary arithmetic: 0 0 0 1 0 1 0 1 15 + 0 0 1 0 0 1 1 1 27 0 0 1 1 1 1 0 0 = 3ch the da instruction adjusts this result so that the correct bcd representation is obtained: 0 0 1 1 1 1 0 0 + 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 = 42 assuming the same values given above, the statements sub 27h,r0 ; c "0", h "0", bits 4?7 = 3, bits 0?3 = 1 da @r1 ; @r1 31?0 leave the value 31 (bcd) in the address 27h (@r1). s3c84bb/f84bb instruction set 6-35 dec ? decrement dec dst operation: dst dst?1 the contents of the destination operand are decremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 00 r 4 01 ir examples: given: r1 = 03h and register 03h = 10h: dec r1 r1 = 02h dec @r1 register 03h = 0fh in the first example, if the working register r1 contains the value 03h, the statement "dec r1" decrements the hexadecimal value by one, leaving the value 02h. in the second example, the statement "dec @r1" decrements the value 10h contained in the destination register 03h by one, leaving the value 0fh. instruction set s3c84bb/f84bb 6-36 decw ? decrement word decw dst operation: dst dst ? 1 the contents of the destination location (which must be an even address) and the operand following that location are treated as a single 16-bit value that is decremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 8 80 rr 8 81 ir examples: given: r0 = 12h, r1 = 34h, r2 = 30h, register 30h = 0fh, and register 31h = 21h: decw rr0 r0 = 12h, r1 = 33h decw @r2 register 30h = 0fh, register 31h = 20h in the first example, the destination register r0 contains the value 12h and the register r1 the value 34h. the statement "decw rr0" addresses r0 and the following operand r1 as a 16-bit word and decrements the value of r1 by one, leaving the value 33h. note: a system malfunction may occur if you use a zero flag (flags.6) result together with a decw instruction. to avoid this problem, it is recommended to use decw as shown in the following example. loop decw rr0 ld r2,r1 or r2,r0 jr nz,loop s3c84bb/f84bb instruction set 6-37 di ? disable interrupts di operation: sym (0) 0 bit zero of the system mode control register, sym.0, is cleared to "0", globally disabling all interrupt processing. interrupt requests will continue to set their respective interrupt pending bits, but the cpu will not service them while interrupt processing is disabled. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 8f example: given: sym = 01h: di if the value of the sym register is 01h, the statement "di" leaves the new value 00h in the register and clears sym.0 to "0", disabling interrupt processing. instruction set s3c84bb/f84bb 6-38 div ? divide (unsigned) div dst,src operation: dst src dst (upper) remainder dst (lower) quotient the destination operand (16 bits) is divided by the source operand (8 bits). the quotient (8 bits) is stored in the lower half of the destination. the remainder (8 bits) is stored in the upper half of the destination. when the quotient is 2 8 , the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect. both operands are treated as unsigned integers. flags: c: set if the v flag is set and the quotient is between 2 8 and 2 9 ?1; cleared otherwise. z: set if the divisor or the quotient = "0"; cleared otherwise. s: set if msb of the quotient = "1"; cleared otherwise. v: set if the quotient is 2 8 or if the divisor = "0"; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 2 6 /10 * 94 rr r 2 6 /10 * 95 rr ir 2 6 /10 * 96 rr im * execution takes 10 cycles if the divide-by-zero is attempted, otherwise, it takes 2 6 cycles. examples: given: r0 = 10h, r1 = 03h, r2 = 40h, register 40h = 80h: div rr0,r2 r0 = 03h, r1 = 40h div rr0,@r2 r0 = 03h, r1 = 20h div rr0,#20h r0 = 03h, r1 = 80h in the first example, the destination working register pair rr0 contains the values 10h (r0) and 03h (r1), and the register r2 contains the value 40h. the statement "div rr0,r2" divides the 16-bit rr0 value by the 8-bit value of the r2 (source) register. after the div instruction, r0 contains the value 03h and r1 contains 40h. the 8-bit remainder is stored in the upper half of the destination register rr0 (r0) and the quotient in the lower half (r1). s3c84bb/f84bb instruction set 6-39 djnz ? decrement and jump if non-zero djnz r,dst operation: r r ? 1 if r 0, pc pc + dst the working register being used as a counter is decremented. if the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the pc. the range of the relative address is + 127 to ? 128, and the original value of the pc is taken to be the address of the instruction byte following the djnz statement. note: in case of using djnz instruction, the working register being used as a counter should be set at the one of location 0c0h to 0cfh with srp, srp0 or srp1 instruction. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst r | opc dst 2 8 (jump taken) ra ra 8 (no jump) r = 0 to f example: given: r1 = 02h and loop is the label of a relative address: srp #0c0h djnz r1,loop djnz is typically used to control a "loop" of instructions. in many cases, a label is used as the destination operand instead of a numeric relative address value. in the example, the working register r1 contains the value 02h, and loop is the label for a relative address. the statement "djnz r1, loop" decrements the register r1 by one, leaving the value 01h. because the contents of r1 after the decrement are non-zero, the jump is taken to the relative address specified by the loop label. instruction set s3c84bb/f84bb 6-40 ei ? enable interrupts ei operation: sym (0) 1 the ei instruction sets bit zero of the system mode register, sym.0 to "1". this allows interrupts to be serviced as they occur (assuming they have the highest priority). if an interrupt's pending bit was set while interrupt processing was disabled (by executing a di instruction), it will be serviced when the ei instruction is executed. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 9f example: given: sym = 00h: ei if the sym register contains the value 00h, that is, if interrupts are currently disabled, the statement "ei" sets the sym register to 01h, enabling all interrupts. (sym.0 is the enable bit for global interrupt processing.) s3c84bb/f84bb instruction set 6-41 enter ? enter enter operation: sp sp ? 2 @sp ip ip pc pc @ip ip ip + 2 this instruction is useful when implementing threaded-code languages. the contents of the instruction pointer are pushed to the stack. the program counter (pc) value is then written to the instruction pointer. the program memory word that is pointed to by the instruction pointer is loaded into the pc, and the instruction pointer is incremented by two. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 14 1f example: the diagram below shows an example of how to use an enter statement. ip data address data 40 41 42 43 address data 1f 01 10 memory stack 0050 before 0022 0040 pc 22 iph ipl data ip address data 40 41 42 43 address data 1f 01 10 memory stack enter address h address l address h 0043 0020 0110 pc enter address h address l address h routine 110 20 21 22 after 00 50 instruction set s3c84bb/f84bb 6-42 exit ? exit exit operation: ip @sp sp sp + 2 pc @ip ip ip + 2 this instruction is useful when implementing threaded-code languages. the stack value is popped and loaded into the instruction pointer. the program memory word that is pointed to by the instruction pointer is then loaded into the program counter, and the instruction pointer is incremented by two. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 16 2f example: the diagram below shows an example of how to use an exit statement. ip data address data 50 51 address data 60 00 memory stack 0050 before 0022 0040 pc 22 iph ipl data ip address data 60 address data memory stack pcl old pch exit 0043 0020 0110 pc main 140 20 21 22 after 00 50 s3c84bb/f84bb instruction set 6-43 idle ? idle operation idle operation: (see description) the idle instruction stops the cpu clock while allowing the system clock oscillation to continue. idle mode can be released by an interrupt request (irq) or an external reset operation. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc 1 4 6f ? ? example: the instruction idle stops the cpu clock but it does not stop the system clock. instruction set s3c84bb/f84bb 6-44 inc ? increment inc dst operation: dst dst + 1 the contents of the destination operand are incremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst dst | opc 1 4 re r r = 0 to f opc dst 2 4 20 r 4 21 ir examples: given: r0 = 1bh, register 00h = 0ch, and register 1bh = 0fh: inc r0 r0 = 1ch inc 00h register 00h = 0dh inc @r0 r0 = 1bh, register 01h = 10h in the first example, if the destination working register r0 contains the value 1bh, the statement "inc r0" leaves the value 1ch in that same register. the second example shows the effect an inc instruction has on the register at the location 00h, assuming that it contains the value 0ch. in the third example, inc is used in indirect register (ir) addressing mode to increment the value of the register 1bh from 0fh to 10h. s3c84bb/f84bb instruction set 6-45 incw ? increment word incw dst operation: dst dst + 1 the contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 8 a0 rr 8 a1 ir examples: given: r0 = 1ah, r1 = 02h, register 02h = 0fh, and register 03h = 0ffh: incw rr0 r0 = 1ah, r1 = 03h incw @r1 register 02h = 10h, register 03h = 00h in the first example, the working register pair rr0 contains the value 1ah in the register r0 and 02h in the register r1. the statement "incw rr0" increments the 16-bit destination by one, leaving the value 03h in the register r1. in the second example, the statement "incw @r1" uses indirect register (ir) addressing mode to increment the contents of the general register 03h from 0ffh to 00h and the register 02h from 0fh to 10h. note: a system malfunction may occur if you use a zero (z) flag (flags.6) result together with an incw instruction. to avoid this problem, it is recommended to use the incw instruction as shown in the following example: loop: incw rr0 ld r2,r1 or r2,r0 jr nz,loop instruction set s3c84bb/f84bb 6-46 iret ? interrupt return iret iret (normal) iret (fast) operation: flags @sp pc ? ip sp sp + 1 flags flags' pc @sp fis 0 sp sp + 2 sym(0) 1 this instruction is used at the end of an interrupt service routine. it restores the flag register and the program counter. it also re-enables global interrupts. a "normal iret" is executed only if the fast interrupt status bit (fis, bit one of the flags register, 0d5h) is cleared (= "0"). if a fast interrupt occurred, iret clears the fis bit that was set at the beginning of the service routine. flags: all flags are restored to their original settings (that is, the settings before the interrupt occurred). format: iret (normal) bytes cycles opcode (hex) opc 1 12 bf iret (fast) bytes cycles opcode (hex) opc 1 6 bf example: in the figure below, the instruction pointer is initially loaded with 100h in the main program before interrupt are enabled. when an interrupt occurs, the program counter and the instruction pointer are swapped. this causes the pc to jump to the address 100h and the ip to keep the return address. the last instruction in the service routine is normally a jump to iret at the address ffh. this loads the instruction pointer with 100h "again" and causes the program counter to jump back to the main program. now, the next interrupt can occur and the ip is still correct at 100h. iret interrupt service routine jp to ffh 0h ffh 100h ffffh note : in the fast interrupt example above, if the last instruction is not a jump to iret, you must pay attention to the order of the last tow instruction. the iret cannot be immediately proceeded by an instruction which clears the interrupt status (as with a reset of the ipr register). s3c84bb/f84bb instruction set 6-47 jp ? jump jp cc,dst (conditional) jp dst (unconditional) operation: if cc is true, pc dst the conditional jump instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true, otherwise, the instruction following the jp instruction is executed. the unconditional jp simply replaces the contents of the pc with the contents of the specified register pair. control then passes to the statement addressed by the pc. flags: no flags are affected. format: (1) (2) bytes cycles opcode (hex) addr mode dst cc | opc dst 3 8 ccd da cc = 0 to f opc dst 2 8 30 irr notes: 1. the 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump. 2. in the first byte of the 3-byte instruction format (conditional jump), the condition code and the opcode are both four bits. examples: given: the carry flag (c) = "1", register 00 = 01h, and register 01 = 20h jp c,label_w label_w = 1000h, pc = 1000h jp @00h pc = 0120h the first example shows a conditional jp. assuming that the carry flag is set to "1", the statement "jp c,label_w" replaces the contents of the pc with the value 1000h and transfers control to that location. had the carry flag not been set, control would then have passed to the statement immediately following the jp instruction. the second example shows an unconditional jp. the statement "jp @00" replaces the contents of the pc with the contents of the register pair 00h and 01h, leaving the value 0120h. instruction set s3c84bb/f84bb 6-48 jr ? jump relative jr cc,dst operation: if cc is true, pc pc + dst if the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter, otherwise, the instruction following the jr instruction is executed. (see the list of condition codes at the beginning of this chapter). the range of the relative address is +127, ?128, and the original value of the program counter is taken to be the address of the first instruction byte following the jr statement. flags: no flags are affected. format: (note) bytes cycles opcode (hex) addr mode dst cc | opc dst 2 6 ccb ra cc = 0 to f note: in the first byte of the two-byte instruction format, the condition code and the opcode are each four bits in length. example: given: the carry flag = "1" and label_x = 1ff7h: jr c,label_x pc = 1ff7h if the carry flag is set (that is, if the condition code is ?true?), the statement "jr c,label_x" will pass control to the statement whose address is currently in the program counter. otherwise, the program instruction following the jr will be executed. s3c84bb/f84bb instruction set 6-49 ld ? load ld dst,src operation: dst src the contents of the source are loaded into the destination. the source's contents are unaffected. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src dst | opc src 2 4 rc r im 4 r8 r r src | opc dst 2 4 r9 r r r = 0 to f opc dst | src 2 4 c7 r lr 4 d7 ir r opc src dst 3 6 e4 r r 6 e5 r ir opc dst src 3 6 e6 r im 6 d6 ir im opc src dst 3 6 f5 ir r opc dst | src x 3 6 87 r x [r] opc src | dst x 3 6 97 x [r] r instruction set s3c84bb/f84bb 6-50 ld ? load ld (continued) examples: given: r0 = 01h, r1 = 0ah, register 00h = 01h, register 01h = 20h, register 02h = 02h, loop = 30h, and register 3ah = 0ffh: ld r0,#10h r0 = 10h ld r0,01h r0 = 20h, register 01h = 20h ld 01h,r0 register 01h = 01h, r0 = 01h ld r1,@r0 r1 = 20h, r0 = 01h ld @r0,r1 r0 = 01h, r1 = 0ah, register 01h = 0ah ld 00h,01h register 00h = 20h, register 01h = 20h ld 02h,@00h register 02h = 20h, register 00h = 01h ld 00h,#0ah register 00h = 0ah ld @00h,#10h register 00h = 01h, register 01h = 10h ld @00h,02h register 00h = 01h, register 01h = 02, register 02h = 02h ld r0,#loop[r1] r0 = 0ffh, r1 = 0ah ld #loop[r0],r1 register 31h = 0ah, r0 = 01h, r1 = 0ah s3c84bb/f84bb instruction set 6-51 ldb ? load bit ldb dst,src.b ldb dst.b,src operation: dst(0) src(b) or dst(b) src(0) the specified bit of the source is loaded into bit zero (lsb) of the destination, or bit zero of the source is loaded into the specified bit of the destination. no other bits of the destination are affected. the source is unaffected. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | b | 0 src 3 6 47 r0 rb opc src | b | 1 dst 3 6 47 rb r0 note: in the second byte of the instruction format, the destination (or the source) address is four bits, the bit address "b" is three bits, and the lsb address value is one bit in length. examples: given: r0 = 06h and general register 00h = 05h: ldb r0,00h.2 r0 = 07h, register 00h = 05h ldb 00h.0,r0 r0 = 06h, register 00h = 04h in the first example, the destination working register r0 contains the value 06h and the source general register 00h the value 05h. the statement "ld r0,00h.2" loads the bit two value of the 00h register into bit zero of the r0 register, leaving the value 07h in the register r0. in the second example, 00h is the destination register. the statement "ld 00h.0,r0" loads bit zero of the register r0 to the specified bit (bit zero) of the destination register, leaving 04h in the general register 00h. instruction set s3c84bb/f84bb 6-52 ldc/lde ? load memory ldc dst,src lde dst,src operation: dst src this instruction loads a byte from program or data memory into a working register or vice-versa. the source values are unaffected. ldc refers to program memory and lde to data memory. the assembler makes "irr" or "rr" values an even number for program memory and an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src 1. opc dst | src 2 10 c3 r irr 2. opc src | dst 2 10 d3 irr r 3. opc dst | src xs 3 12 e7 r xs [rr] 4. opc src | dst xs 3 12 f7 xs [rr] r 5. opc dst | src xl l xl h 4 14 a7 r xl [rr] 6. opc src | dst xl l xl h 4 14 b7 xl [rr] r 7. opc dst | 0000 da l da h 4 14 a7 r da 8. opc src | 0000 da l da h 4 14 b7 da r 9. opc dst | 0001 da l da h 4 14 a7 r da 10. opc src | 0001 da l da h 4 14 b7 da r notes: 1. the source (src) or the working register pair [rr] for formats 5 and 6 cannot use the register pair 0?1. 2. for the formats 3 and 4, the destination "xs [rr]" and the source address "xs [rr]" are both one byte. 3. for the formats 5 and 6, the destination "xl [rr] and the source address "xl [rr]" are both two bytes. 4. the da and the r source values for the formats 7 and 8 are used to address program memory. the second set of values, used in the formats 9 and 10, are used to address data memory. 5. lde instruction can be used to read/write the data of 64-kbyte data memory. s3c84bb/f84bb instruction set 6-53 ldc/lde ? load memory ldc/lde (continued) examples: given: r0 = 11h, r1 = 34h, r2 = 01h, r3 = 04h; program memory locations 0103h = 4fh, 0104h = 1a, 0105h = 6dh, and 1104h = 88h. external data memory locations 0103h = 5fh, 0104h = 2ah, 0105h = 7dh, and 1104h = 98h: ldc r0,@rr2 ; r0 contents of program memory location 0104h; ; r0 = 1ah, r2 = 01h, r3 = 04h lde r0,@rr2 ; r0 contents of external data memory location 0104h; ; r0 = 2ah, r2 = 01h, r3 = 04h ldc @rr2,r0 ; 11h (contents of r0) is loaded into program memory ; location 0104h (rr2); r0, r2, r3 no change lde @rr2,r0 ; 11h (contents of r0) is loaded into external data memory ; location 0104h (rr2); r0, r2, r3 no change ldc r0,#01h[rr2] ; r0 contents of program memory location 0105h ; (01h + rr2); r0 = 6dh, r2 = 01h, r3 = 04h lde r0,#01h[rr2] ; r0 contents of external data memory location 0105h ; (01h + rr2); r0 = 7dh, r2 = 01h, r3 = 04h ldc #01h[rr2],r0 ; 11h (contents of r0) is loaded into program memory location ; 0105h (01h + 0104h) lde #01h[rr2],r0 ; 11h (contents of r0) is loaded into external data memory ; location 0105h (01h + 0104h) ldc r0,#1000h[rr2] ; r0 contents of program memory location 1104h ; (1000h + 0104h); r0 = 88h, r2 = 01h, r3 = 04h lde r0,#1000h[rr2] ; r0 contents of external data memory location 1104h ; (1000h + 0104h); r0 = 98h, r2 = 01h, r3 = 04h ldc r0,1104h ; r0 contents of program memory location 1104h ; r0 = 88h lde r0,1104h ; r0 contents of external data memory location 1104h; ; r0 = 98h ldc 1105h,r0 ; 11h (contents of r0) is loaded into program memory location ; 1105h; (1105h) 11h lde 1105h,r0 ; 11h (contents of r0) is loaded into external data memory ; location 1105h; (1105h) 11h note: the ldc and the lde instructions are not supported by masked rom type devices. instruction set s3c84bb/f84bb 6-54 ldcd/lded ? load memory and decrement ldcd dst,src lded dst,src operation: dst src rr rr ? 1 these instructions are used for user stacks or block transfers of data from program or data memory to the register file. the address of the memory location is specified by a working register pair. the contents of the source location are loaded into the destination location. the memory address is then decremented. the contents of the source are unaffected. ldcd refers to program memory and lded refers to external data memory. the assembler makes "irr" an even number for program memory and an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 10 e2 r irr examples: given: r6 = 10h, r7 = 33h, r8 = 12h, program memory location 1033h = 0cdh, and external data memory location 1033h = 0ddh: ldcd r8,@rr6 ; 0cdh (contents of program memory location 1033h) is loaded ; into r8 and rr6 is decremented by one; ; r8 = 0cdh, r6 = 10h, r7 = 32h (rr6 rr6 ? 1) lded r8,@rr6 ; 0ddh (contents of data memory location 1033h) is loaded ; into r8 and rr6 is decremented by one (rr6 rr6 ? 1); ; r8 = 0ddh, r6 = 10h, r7 = 32h note: lded instruction can be used to read/write the data of 64-kbyte data memory. s3c84bb/f84bb instruction set 6-55 ldci/ldei ? load memory and increment ldci dst,src ldei dst,src operation: dst src rr rr + 1 these instructions are used for user stacks or block transfers of data from program or data memory to the register file. the address of the memory location is specified by a working register pair. the contents of the source location are loaded into the destination location. the memory address is then incremented automatically. the contents of the source are unaffected. ldci refers to program memory and ldei refers to external data memory. the assembler makes "irr" an even number for program memory and an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 10 e3 r irr examples: given: r6 = 10h, r7 = 33h, r8 = 12h, program memory locations 1033h = 0cdh and 1034h = 0c5h; external data memory locations 1033h = 0ddh and 1034h = 0d5h: ldci r8,@rr6 ; 0cdh (contents of program memory location 1033h) is loaded ; into r8 and rr6 is incremented by one (rr6 rr6 + 1); ; r8 = 0cdh, r6 = 10h, r7 = 34h ldei r8,@rr6 ; 0ddh (contents of data memory location 1033h) is loaded ; into r8 and rr6 is incremented by one (rr6 rr6 + 1); ; r8 = 0ddh, r6 = 10h, r7 = 34h note: ldei instruction can be used to read/write the data of 64-kbyte data memory. ` instruction set s3c84bb/f84bb 6-56 ldcpd/ldepd ? load memory with pre-decrement ldcpd dst,src ldepd dst,src operation: rr rr ? 1 dst src these instructions are used for block transfers of data from program or data memory to the register file. the address of the memory location is specified by a working register pair and is first decremented. the contents of the source location are then loaded into the destination location. the contents of the source are unaffected. ldcpd refers to program memory and ldepd refers to external data memory. the assembler makes "irr" an even number for program memory and an odd number for external data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src | dst 2 14 f2 irr r examples: given: r0 = 77h, r6 = 30h, and r7 = 00h: ldcpd @rr6,r0 ; (rr6 rr6 ? 1) ; 77h (the contents of r0) is loaded into program memory ; location 2fffh (3000h ? 1h); ; r0 = 77h, r6 = 2fh, r7 = 0ffh ldepd @rr6,r0 ; (rr6 rr6 ? 1) ; 77h (the contents of r0) is loaded into external data memory ; location 2fffh (3000h ? 1h); note: ldepd instruction can be used to read/write the data of 64-kbyte data memory. s3c84bb/f84bb instruction set 6-57 ldcpi/ldepi ? load memory with pre-increment ldcpi dst,src ldepi dst,src operation: rr rr + 1 dst src these instructions are used for block transfers of data from program or data memory to the register file. the address of the memory location is specified by a working register pair and is first incremented. the contents of the source location are loaded into the destination location. the contents of the source are unaffected. ldcpi refers to program memory and ldepi refers to external data memory. the assembler makes "irr" an even number for program memory and an odd number for data memory. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src | dst 2 14 f3 irr r examples: given: r0 = 7fh, r6 = 21h, and r7 = 0ffh: ldcpi @rr6,r0 ; (rr6 brr6 + 1) ; 7fh (the contents of r0) is loaded into program memory ; location 2200h (21ffh + 1h); ; r0 = 7fh, r6 = 22h, r7 = 00h ldepi @rr6,r0 ; (rr6 brr6 + 1) ; 7fh (the contents of r0) is loaded into external data memory ; location 2200h (21ffh + 1h); ; r0 = 7fh, r6 = 22h, r7 = 00h note: ldepi instruction can be used to read/write the data of 64-kbyte data memory. instruction set s3c84bb/f84bb 6-58 ldw ? load word ldw dst,src operation: dst src the contents of the source (a word) are loaded into the destination. the contents of the source are unaffected. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 8 c4 rr rr 8 c5 rr ir opc dst src 4 8 c6 rr iml examples: given: r4 = 06h, r5 = 1ch, r6 = 05h, r7 = 02h, register 00h = 1ah, register 01h = 02h, register 02h = 03h,and register 03h = 0fh ldw rr6,rr4 r6 = 06h, r7 = 1ch, r4 = 06h, r5 = 1ch ldw 00h,02h register 00h = 03h, register 01h = 0fh, register 02h = 03h, register 03h = 0fh ldw rr2,@r7 r2 = 03h, r3 = 0fh, ldw 04h,@01h register 04h = 03h, register 05h = 0fh ldw rr6,#1234h r6 = 12h, r7 = 34h ldw 02h,#0fedh register 02h = 0fh, register 03h = 0edh in the second example, please note that the statement "ldw 00h,02h" loads the contents of the source word 02h and 03h into the destination word 00h and 01h. this leaves the value 03h in the general register 00h and the value 0fh in the register 01h. other examples show how to use the ldw instruction with various addressing modes and formats. s3c84bb/f84bb instruction set 6-59 mult ? multiply (unsigned) mult dst,src operation: dst dst src the 8-bit destination operand (the even numbered register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address. both operands are treated as unsigned integers. flags: c: set if the result is > 255; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if msb of the result is a "1"; cleared otherwise. v: cleared. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 22 84 rr r 22 85 rr ir 22 86 rr im examples: given: register 00h = 20h, register 01h = 03h, register 02h = 09h, register 03h = 06h: mult 00h, 02h register 00h = 01h, register 01h = 20h, register 02h = 09h mult 00h, @01h register 00h = 00h, register 01h = 0c0h mult 00h, #30h register 00h = 06h, register 01h = 00h in the first example, the statement "mult 00h,02h" multiplies the 8-bit destination operand (in the register 00h of the register pair 00h, 01h) by the source register 02h operand (09h). the 16-bit product, 0120h, is stored in the register pair 00h, 01h. instruction set s3c84bb/f84bb 6-60 next ? next next operation: pc @ip ip ip + 2 the next instruction is useful when implementing threaded-code languages. the program memory word that is pointed to by the instruction pointer is loaded into the program counter. the instruction pointer is then incremented by two. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 10 0f example: the following diagram shows an example of how to use the next instruction. s3c84bb/f84bb instruction set 6-61 nop ? no operation nop operation: no action is performed when the cpu executes this instruction. typically, one or more nops are executed in sequence in order to affect a timing delay of variable duration. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 ff example: when the instruction nop is executed in a program, no operation occurs. instead, there happens a delay in instruction execution time which is of approximately one machine cycle per each nop instruction encountered. instruction set s3c84bb/f84bb 6-62 or ? logical or or dst,src operation: dst dst or src the source operand is logically ored with the destination operand and the result is stored in the destination. the contents of the source are unaffected. the or operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1", otherwise, a "0" is stored. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 42 r r 6 43 r lr opc src dst 3 6 44 r r 6 45 r ir opc dst src 3 6 46 r im examples: given: r0 = 15h, r1 = 2ah, r2 = 01h, register 00h = 08h, register 01h = 37h, and register 08h = 8ah or r0,r1 r0 = 3fh, r1 = 2ah or r0,@r2 r0 = 37h, r2 = 01h, register 01h = 37h or 00h,01h register 00h = 3fh, register 01h = 37h or 01h,@00h register 00h = 08h, register 01h = 0bfh or 00h,#02h register 00h = 0ah in the first example, if the working register r0 contains the value 15h and the register r1 the value 2ah, the statement "or r0,r1" logical-ors the r0 and r1 register contents and stores the result (3fh) in the destination register r0. other examples show the use of the logical or instruction with various addressing modes and formats. s3c84bb/f84bb instruction set 6-63 pop ? pop from stack pop dst operation: dst @sp sp sp + 1 the contents of the location addressed by the stack pointer are loaded into the destination. the stack pointer is then incremented by one. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 8 50 r 8 51 ir examples: given: register 00h = 01h, register 01h = 1bh, sph (0d8h) = 00h, spl (0d9h) = 0fbh, and stack register 0fbh = 55h: pop 00h register 00h = 55h, sp = 00fch pop @00h register 00h = 01h, register 01h = 55h, sp = 00fch in the first example, the general register 00h contains the value 01h. the statement "pop 00h" loads the contents of the location 00fbh (55h) into the destination register 00h and then increments the stack pointer by one. the register 00h then contains the value 55h and the sp points to the location 00fch. instruction set s3c84bb/f84bb 6-64 popud ? pop user stack (decrementing) popud dst,src operation: dst src ir ir ? 1 this instruction is used for user-defined stacks in the register file. the contents of the register file location addressed by the user stack pointer are loaded into the destination. the user stack pointer is then decremented. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 8 92 r ir example: given: register 00h = 42h (user stack pointer register), register 42h = 6fh, and register 02h = 70h: popud 02h,@00h register 00h = 41h, register 02h = 6fh, register 42h = 6fh if the general register 00h contains the value 42h and the register 42h the value 6fh, the statement "popud 02h,@00h" loads the contents of the register 42h into the destination register. the user stack pointer is then decremented by one, leaving the value 41h. s3c84bb/f84bb instruction set 6-65 popui ? pop user stack (incrementing) popui dst,src operation: dst src ir ir + 1 the popui instruction is used for user-defined stacks in the register file. the contents of the register file location addressed by the user stack pointer are loaded into the destination. the user stack pointer is then incremented. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc src dst 3 8 93 r ir example: given: register 00h = 01h and register 01h = 70h: popui 02h,@00h register 00h = 02h, register 01h = 70h, register 02h = 70h if the general register 00h contains the value 01h and the register 01h the value 70h, the statement "popui 02h,@00h" loads the value 70h into the destination general register 02h. the user stack pointer (the register 00h) is then incremented by one, changing its value from 01h to 02h. instruction set s3c84bb/f84bb 6-66 push ? push to stack push src operation: sp sp ? 1 @sp src a push instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. the operation then adds the new value to the top of the stack. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst opc src 2 8 (internal clock) 70 r 8 (external clock) 8 (internal clock) 8 (external clock) 71 ir examples: given: register 40h = 4fh, register 4fh = 0aah, sph = 00h, and spl = 00h: push 40h register 40h = 4fh, stack register 0ffh = 4fh, sph = 0ffh, spl = 0ffh push @40h register 40h = 4fh, register 4fh = 0aah, stack register 0ffh = 0aah, sph = 0ffh, spl = 0ffh in the first example, if the stack pointer contains the value 0000h, and the general register 40h the value 4fh, the statement "push 40h" decrements the stack pointer from 0000 to 0ffffh. it then loads the contents of the register 40h into the location 0ffffh and adds this new value to the top of the stack. s3c84bb/f84bb instruction set 6-67 pushud ? push user stack (decrementing) pushud dst,src operation: ir ir ? 1 dst src this instruction is used to address user-defined stacks in the register file. pushud decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst src 3 8 82 ir r example: given: register 00h = 03h, register 01h = 05h, and register 02h = 1ah: pushud @00h,01h register 00h = 02h, register 01h = 05h, register 02h = 05h if the user stack pointer (the register 00h, for example) contains the value 03h, the statement "pushud @00h,01h" decrements the user stack pointer by one, leaving the value 02h. the 01h register value, 05h, is then loaded into the register addressed by the decremented user stack pointer. instruction set s3c84bb/f84bb 6-68 pushui ? push user stack (incrementing) pushui dst,src operation: ir ir + 1 dst src this instruction is used for user-defined stacks in the register file. pushui increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc dst src 3 8 83 ir r example: given: register 00h = 03h, register 01h = 05h, and register 04h = 2ah: pushui @00h,01h register 00h = 04h, register 01h = 05h, register 04h = 05h if the user stack pointer (the register 00h, for example) contains the value 03h, the statement "pushui @00h,01h" increments the user stack pointer by one, leaving the value 04h. the 01h register value, 05h, is then loaded into the location addressed by the incremented user stack pointer. s3c84bb/f84bb instruction set 6-69 rcf ? reset carry flag rcf rcf operation: c 0 the carry flag is cleared to logic zero, regardless of its previous value. flags: c: cleared to "0". no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 cf example: given: c = "1" or "0": the instruction rcf clears the carry flag (c) to logic zero. instruction set s3c84bb/f84bb 6-70 ret ? return ret operation: pc @sp sp sp + 2 the ret instruction is normally used to return to the previously executed procedure at the end of the procedure entered by a call instruction. the contents of the location addressed by the stack pointer are popped into the program counter. the next statement to be executed is the one that is addressed by the new program counter value. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 10 af example: given: sp = 00fch, (sp) = 101ah, and pc = 1234: ret pc = 101ah, sp = 00feh the ret instruction pops the contents of the stack pointer location 00fch (10h) into the high byte of the program counter. the stack pointer then pops the value in the location 00feh (1ah) into the pc's low byte and the instruction at the location 101ah is executed. the stack pointer now points to the memory location 00feh. s3c84bb/f84bb instruction set 6-71 rl ? rotate left rl dst operation: c dst (7) dst (0) dst (7) dst (n + 1) dst (n), n = 0?6 the contents of the destination operand are rotated left one bit position. the initial value of bit 7 is moved to the bit zero (lsb) position and also replaces the carry flag, as shown in the figure below. 70 c flags: c: set if the bit rotated from the most significant bit position (bit 7) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 90 r 4 91 ir examples: given: register 00h = 0aah, register 01h = 02h and register 02h = 17h: rl 00h register 00h = 55h, c = "1" rl @01h register 01h = 02h, register 02h = 2eh, c = "0" in the first example, if the general register 00h contains the value 0aah (10101010b), the statement "rl 00h" rotates the 0aah value left one bit position, leaving the new value 55h (01010101b) and setting the carry (c) and the overflow (v) flags. instruction set s3c84bb/f84bb 6-72 rlc ? rotate left through carry rlc dst operation: dst (0) c c dst (7) dst (n + 1) dst (n), n = 0?6 the contents of the destination operand with the carry flag are rotated left one bit position. the initial value of bit 7 replaces the carry flag (c), and the initial value of the carry flag replaces bit zero. 70 c flags: c: set if the bit rotated from the most significant bit position (bit 7) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination is changed during the rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 10 r 4 11 ir examples: given: register 00h = 0aah, register 01h = 02h, and register 02h = 17h, c = "0": rlc 00h register 00h = 54h, c = "1" rlc @01h register 01h = 02h, register 02h = 2eh, c = "0" in the first example, if the general register 00h has the value 0aah (10101010b), the statement "rlc 00h" rotates 0aah one bit position to the left. the initial value of bit 7 sets the carry flag and the initial value of the c flag replaces bit zero of the register 00h, leaving the value 55h (01010101b). the msb of the register 00h resets the carry flag to "1" and sets the overflow flag. s3c84bb/f84bb instruction set 6-73 rr ? rotate right rr dst operation: c dst (0) dst (7) dst (0) dst (n) dst (n + 1), n = 0?6 the contents of the destination operand are rotated right one bit position. the initial value of bit zero (lsb) is moved to bit 7 (msb) and also replaces the carry flag (c). 70 c flags: c: set if the bit rotated from the least significant bit position (bit zero) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination is changed during the rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 e0 r 4 e1 ir examples: given: register 00h = 31h, register 01h = 02h, and register 02h = 17h: rr 00h register 00h = 98h, c = "1" rr @01h register 01h = 02h, register 02h = 8bh, c = "1" in the first example, if the general register 00h contains the value 31h (00110001b), the statement "rr 00h" rotates this value one bit position to the right. the initial value of bit zero is moved to bit 7, leaving the new value 98h (10011000b) in the destination register. the initial bit zero also resets the c flag to "1" and the sign flag and the overflow flag are also set to "1". instruction set s3c84bb/f84bb 6-74 rrc ? rotate right through carry rrc dst operation: dst (7) c c dst (0) dst (n) dst (n + 1), n = 0?6 the contents of the destination operand and the carry flag are rotated right one bit position. the initial value of bit zero (lsb) replaces the carry flag, and the initial value of the carry flag replaces bit 7 (msb). 70 c flags: c: set if the bit rotated from the least significant bit position (bit zero) was "1". z: set if the result is "0" cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the sign of the destination is changed during the rotation; cleared otherwise. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 c0 r 4 c1 ir examples: given: register 00h = 55h, register 01h = 02h, register 02h = 17h, and c = "0": rrc 00h register 00h = 2ah, c = "1" rrc @01h register 01h = 02h, register 02h = 0bh, c = "1" in the first example, if the general register 00h contains the value 55h (01010101b), the statement "rrc 00h" rotates this value one bit position to the right. the initial value of bit zero ("1") replaces the carry flag and the initial value of the c flag ("1") replaces bit 7. this leaves the new value 2ah (00101010b) in the destination register 00h. the sign flag and the overflow flag are both cleared to "0". s3c84bb/f84bb instruction set 6-75 sb0 ? select bank 0 sb0 operation: bank 0 the sb0 instruction clears the bank address flag in the flags register (flags.0) to logic zero, selecting the bank 0 register addressing in the set 1 area of the register file. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 4f example: the statement sb0 clears flags.0 to "0", selecting the bank 0 register addressing. instruction set s3c84bb/f84bb 6-76 sb1 ? select bank 1 sb1 operation: bank 1 the sb1 instruction sets the bank address flag in the flags register (flags.0) to logic one, selecting the bank 1 register addressing in the set 1 area of the register file. note: bank 1 is not implemented in some ks88-series microcontrollers. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4 5f example: the statement sb1 sets flags.0 to ?1?, selecting the bank 1 register addressing (if bank 1 is implemented in the microcontroller?s internla register file). s3c84bb/f84bb instruction set 6-77 sbc ? subtract with carry sbc dst,src operation: dst dst ? src ? c the source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. the contents of the source are unaffected. subtraction is performed by adding the two's-complement of the source operand to the destination operand. in multiple precision arithmetic, this instruction permits the carry ("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of high-order operands. flags: c: set if a borrow occurred (src > dst); cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign of the result is the same as the sign of the source; cleared otherwise. d: always set to "1". h: cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise, indicating a ?borrow? format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 32 r r 6 33 r lr opc src dst 3 6 34 r r 6 35 r ir opc dst src 3 6 36 r im examples: given: r1 = 10h, r2 = 03h, c = "1", register 01h = 20h, register 02h = 03h, and register 03h = 0ah: sbc r1,r2 r1 = 0ch, r2 = 03h sbc r1,@r2 r1 = 05h, r2 = 03h, register 03h = 0ah sbc 01h,02h register 01h = 1ch, register 02h = 03h sbc 01h,@02h register 01h = 15h, register 02h = 03h, register 03h = 0ah sbc 01h,#8ah register 01h = 95h; c, s, and v = "1" in the first example, if the working register r1 contains the value 10h and the register r2 the value 03h, the statement "sbc r1,r2" subtracts the source value (03h) and the c flag value ("1") from the destination (10h) and then stores the result (0ch) in the register r1. instruction set s3c84bb/f84bb 6-78 scf ? set carry flag scf operation: c 1 the carry flag (c) is set to logic one, regardless of its previous value. flags: c: set to "1". no other flags are affected. format: bytes cycles opcode (hex) opc 1 4 df example: the statement scf sets the carry flag to ?1?. s3c84bb/f84bb instruction set 6-79 sra ? shift right arithmetic sra dst operation: dst (7) dst (7) c dst (0) dst (n) dst (n + 1), n = 0?6 an arithmetic shift-right of one bit position is performed on the destination operand. bit zero (the lsb) replaces the carry flag. the value of bit 7 (the sign bit) is unchanged and is shifted into the bit position 6. 70 c 6 flags: c: set if the bit shifted from the lsb position (bit zero) was "1". z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 d0 r 4 d1 ir examples: given: register 00h = 9ah, register 02h = 03h, register 03h = 0bch, and c = "1": sra 00h register 00h = 0cd, c = "0" sra @02h register 02h = 03h, register 03h = 0deh, c = "0" in the first example, if the general register 00h contains the value 9ah (10011010b), the statement "sra 00h" shifts the bit values in the register 00h right one bit position. bit zero ("0") clears the c flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). this leaves the value 0cdh (11001101b) in the destination register 00h. instruction set s3c84bb/f84bb 6-80 srp/srp0/srp1 ? set register pointer srp src srp0 src srp1 src operation: if src (1) = 1 and src (0) = 0 then: rp0 (3?7) src (3?7) if src (1) = 0 and src (0) = 1 then: rp1 (3?7) src (3?7) if src (1) = 0 and src (0) = 0 then: rp0 (4?7) src (4?7), rp0 (3) 0 rp1 (4?7) src (4?7), rp1 (3) 1 the source data bits one and zero (lsb) determine whether to write one or both of the register pointers, rp0 and rp1. bits 3?7 of the selected register pointer are written unless both register pointers are selected. rp0.3 is then cleared to logic zero and rp1.3 is set to logic one. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode src opc src 2 4 31 im examples: the statement srp #40h sets the register pointer 0 (rp0) at the location 0d6h to 40h and the register pointer 1 (rp1) at the location 0d7h to 48 h. the statement "srp0 #50h" would set rp0 to 50h, and the statement "srp1 #68h" would set rp1 to 68h. note: before execute the stop instruction, you must set the stpcon register as ?10100101b?. otherwise the stop instruction will not execute. s3c84bb/f84bb instruction set 6-81 stop ? stop operation stop operation: the stop instruction stops the both the cpu clock and system clock and causes the microcontroller to enter stop mode. during stop mode, the contents of on-chip cpu registers, peripheral registers, and i/o port control and data registers are retained. stop mode can be released by an external reset operation or by external interrupts. for the reset operation, the reset pin must be held to low level until the required oscillation stabilization interval has elapsed. flags: no flags are affected. format: bytes cycles opcode (hex) addr mode dst src opc 1 4 7f ? ? example: the statement stop halts all microcontroller operations. instruction set s3c84bb/f84bb 6-82 sub ? subtract sub dst,src operation: dst dst ? src the source operand is subtracted from the destination operand and the result is stored in the destination. the contents of the source are unaffected. subtraction is performed by adding the two's complement of the source operand to the destination operand. flags: c: set if a "borrow" occurred; cleared otherwise. z: set if the result is "0"; cleared otherwise. s: set if the result is negative; cleared otherwise. v: set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise. d: always set to "1". h: cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise indicating a ?borrow?. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 22 r r 6 23 r lr opc src dst 3 6 24 r r 6 25 r ir opc dst src 3 6 26 r im examples: given: r1 = 12h, r2 = 03h, register 01h = 21h, register 02h = 03h, register 03h = 0ah: sub r1,r2 r1 = 0fh, r2 = 03h sub r1,@r2 r1 = 08h, r2 = 03h sub 01h,02h register 01h = 1eh, register 02h = 03h sub 01h,@02h register 01h = 17h, register 02h = 03h sub 01h,#90h register 01h = 91h; c, s, and v = "1" sub 01h,#65h register 01h = 0bch; c and s = "1", v = "0" in the first example, if he working register r1 contains the value 12h and if the register r2 contains the value 03h, the statement "sub r1,r2" subtracts the source value (03h) from the destination value (12h) and stores the result (0fh) in the destination register r1. s3c84bb/f84bb instruction set 6-83 swap ? swap nibbles swap dst operation: dst (0 ? 3) ? dst (4 ? 7) the contents of the lower four bits and the upper four bits of the destination operand are swapped. 70 4 3 flags: c: undefined. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: undefined. d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst opc dst 2 4 f0 r 4 f1 ir examples: given: register 00h = 3eh, register 02h = 03h, and register 03h = 0a4h: swap 00h register 00h = 0e3h swap @02h register 02h = 03h, register 03h = 4ah in the first example, if the general register 00h contains the value 3eh (00111110b), the statement "swap 00h" swaps the lower and the upper four bits (nibbles) in the 00h register, leaving the value 0e3h (11100011b). instruction set s3c84bb/f84bb 6-84 tcm ? test complement under mask tcm dst,src operation: (not dst) and src this instruction tests selected bits in the destination operand for a logic one value. the bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). the tcm statement complements the destination operand, which is then anded with the source mask. the zero (z) flag can then be checked to determine the result. the destination and the source operands are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always cleared to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 62 r r 6 63 r lr opc src dst 3 6 64 r r 6 65 r ir opc dst src 3 6 66 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 12h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: tcm r0,r1 r0 = 0c7h, r1 = 02h, z = "1" tcm r0,@r1 r0 = 0c7h, r1 = 02h, register 02h = 23h, z = "0" tcm 00h,01h register 00h = 2bh, register 01h = 02h, z = "1" tcm 00h,@01h register 00h = 2bh, register 01h = 02h, register 02h = 23h, z = "1" tcm 00h,#34 register 00h = 2bh, z = "0" in the first example, if the working register r0 contains the value 0c7h (11000111b) and the register r1 the value 02h (00000010b), the statement "tcm r0,r1" tests bit one in the destination register for a "1" value. because the mask value corresponds to the test bit, the z flag is set to logic one and can be tested to determine the result of the tcm operation. s3c84bb/f84bb instruction set 6-85 tm ? test under mask tm dst,src operation: dst and src this instruction tests selected bits in the destination operand for a logic zero value. the bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is anded with the destination operand. the zero (z) flag can then be checked to determine the result. the destination and the source operands are unaffected. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 72 r r 6 73 r lr opc src dst 3 6 74 r r 6 75 r ir opc dst src 3 6 76 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 18h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: tm r0,r1 r0 = 0c7h, r1 = 02h, z = "0" tm r0,@r1 r0 = 0c7h, r1 = 02h, register 02h = 23h, z = "0" tm 00h,01h register 00h = 2bh, register 01h = 02h, z = "0" tm 00h,@01h register 00h = 2bh, register 01h = 02h, register 02h = 23h, z = "0" tm 00h,#54h register 00h = 2bh, z = "1" in the first example, if the working register r0 contains the value 0c7h (11000111b) and the register r1 the value 02h (00000010b), the statement "tm r0,r1" tests bit one in the destination register for a "0" value. because the mask value does not match the test bit, the z flag is cleared to logic zero and can be tested to determine the result of the tm operation. instruction set s3c84bb/f84bb 6-86 wfi ? wait for interrupt wfi operation: the cpu is effectively halted before an interrupt occurs, except that dma transfers can still take place during this wait state. the wfi status can be released by an internal interrupt, including a fast interrupt. flags: no flags are affected. format: bytes cycles opcode (hex) opc 1 4n 3f ( n = 1, 2, 3, ? ) example: the following sample program structure shows the sequence of operations that follow a "wfi" statement: ei wfi (next instruction) main program . . . . . . interrupt occurs interrupt service routine . . . clear interrupt flag iret service routine completed (enable global interrupt) (wait for interrupt) s3c84bb/f84bb instruction set 6-87 xor ? logical exclusive or xor dst,src operation: dst dst xor src the source operand is logically exclusive-ored with the destination operand and the result is stored in the destination. the exclusive-or operation results in a "1" bit being stored whenever the corresponding bits in the operands are different. otherwise, a "0" bit is stored. flags: c: unaffected. z: set if the result is "0"; cleared otherwise. s: set if the result bit 7 is set; cleared otherwise. v: always reset to "0". d: unaffected. h: unaffected. format: bytes cycles opcode (hex) addr mode dst src opc dst | src 2 4 b2 r r 6 b3 r lr opc src dst 3 6 b4 r r 6 b5 r ir opc dst src 3 6 b6 r im examples: given: r0 = 0c7h, r1 = 02h, r2 = 18h, register 00h = 2bh, register 01h = 02h, and register 02h = 23h: xor r0,r1 r0 = 0c5h, r1 = 02h xor r0,@r1 r0 = 0e4h, r1 = 02h, register 02h = 23h xor 00h,01h register 00h = 29h, register 01h = 02h xor 00h,@01h register 00h = 08h, register 01h = 02h, register 02h = 23h xor 00h,#54h register 00h = 7fh in the first example, if the working register r0 contains the value 0c7h and if the register r1 contains the value 02h, the statement "xor r0,r1" logically exclusive-ors the r1 value with the r0 value and stores the result (0c5h) in the destination register r0. instruction set s3c84bb/f84bb 6-88 notes s3c84bb/f84bb clock circuit 7-1 clock circuit overview the clock frequency generated for the s3c84bb/f84bb by an external crystal can range from 1 mhz to 12 mhz. the maximum cpu clock frequency is 12 mhz. the x in and x out pins connect the external oscillator or clock source to the on-chip clock circuit. system clock circuit the system clock circuit has the following components: ? external crystal or ceramic resonator oscillation source (or an external clock source) ? oscillator stop and wake-up functions ? programmable frequency divider for the cpu clock (fxx divided by 1, 2, 8, or 16) ? system clock control register, clkcon x in x out c1 c2 s3c84bb/ f84bb figure 7-1. main oscillator circuit (crystal or ceramic oscillator) clock circuit s3c84bb/f84bb 7-2 clock status during power-down modes the two power-down modes, stop mode and idle mode, affect the system clock as follows: ? in stop mode, the main oscillator is halted. stop mode is released, and the oscillator started, by a reset operation or an external interrupt (with rc delay noise filter), and can be released by internal interrupt too when the sub-system oscillator is running and watch timer is operating with sub-system clock. ? in idle mode, the internal clock signal is gated to the cpu, but not to interrupt structure, timers and timer/ counters. idle mode is released by a reset or by an external or internal interrupt. main-system oscillator circuit fxx cpu peri selector 2 1/8-1/4096 frequency dividing circuit 1/2 1/8 1/16 1/1 clkcon.4-.3 idle instruction stop instruction figure 7-2. system clock circuit diagram s3c84bb/f84bb clock circuit 7-3 system clock control register (clkcon) the system clock control register, clkcon, is located in the bank 0 of set 1, address d4h. it is read/write addressable and has the following functions: ? oscillator frequency divide-by value after the main oscillator is activated, and the fxx/16 (the slowest clock speed) is selected as the cpu clock. if necessary, you can then increase the cpu clock speed to f xx /8, f xx /2, or f xx /1. system clock control register (clkcon) d4h, set 1, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 not used (must keep always 0) not used (must keep always 0) divide-by selection bits for cpu clock frequency: 00 = fxx/16 01 = fxx/8 10 = fxx/2 11 = fxx/1 (non-divided) figure 7-3. system clock control register (clkcon) clock circuit s3c84bb/f84bb 7-4 notes s3c84bb/f84bb reset and power-down 8-1 reset and power-down system reset overview during a power-on reset, the voltage at v dd goes to high level and the reset pin is forced to low level. the reset signal is input through a schmitt trigger circuit where it is then synchronized with the cpu clock. this procedure brings s3c84bb/f84bb into a known operating status. to allow time for internal cpu clock oscillation to stabilize, the reset pin must be held to low level for a minimum time interval after the power supply comes within tolerance. the minimum required oscillation stabilization time for a reset operation is 1 millisecond. whenever a reset occurs during normal operation (that is, when both v dd and reset are high level), the reset pin is forced low and the reset operation starts. all system and peripheral control registers are then reset to their default hardware values. in summary, the following sequence of events occurs during a reset operation: ? interrupt is disabled. ? the watchdog function (basic timer) is enabled. ? ports 0-8 are set to input mode. ? peripheral control and data registers are disabled and reset to their default hardware values. ? the program counter (pc) is loaded with the program reset address in the rom, 0100h. ? when the programmed oscillation stabilization time interval has elapsed, the instruction stored in rom location 0100h (and 0101h) is fetched and executed. normal mode reset operation in normal (masked rom) mode, the test pin is tied to v ss . a reset enables access to the 64-kbyte on-chip rom. note to program the duration of the oscillation stabilization interval, you make the appropriate settings to the basic timer control register, btcon, before entering stop mode. also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing '1010b' to the upper nibble of btcon. reset and power-down s3c84bb/f84bb 8-2 hardware reset values table 8-1, 8-2, 8-3 list the reset values for cpu and system registers, peripheral control registers, and peripheral data registers following a reset operation. the following notation is used to represent reset values: ? a "1" or a "0" shows the reset bit value as logic one or logic zero, respectively. ? an "x" means that the bit value is undefined after a reset. ? a dash ("?") means that the bit is either not used or not mapped, but read 0 is the bit value. table 8-1. s3c84bb/f84bb set 1 register values after reset address bit values after reset register name mnemonic dec hex 7 6 5 4 3 2 1 0 timer b control register tbcon 208 d0h 0 0 0 0 0 0 0 0 timer b data register (high byte) tbdatah 209 d1h 1 1 1 1 1 1 1 1 timer b data register (low byte) tbdatal 210 d2h 1 1 1 1 1 1 1 1 basic timer control register btcon 211 d3h 0 0 0 0 0 0 0 0 clock control register clkcon 212 d4h 0 0 0 0 0 0 0 0 system flags register flags 213 d5h x x x x x x 0 0 register pointer 0 rp0 214 d6h 1 1 0 0 0 ? ? ? register pointer 1 rp1 215 d7h 1 1 0 0 1 ? ? ? stack pointer (high byte) sph 216 d8h x x x x x x x x stack pointer (low byte) spl 217 d9h x x x x x x x x instruction pointer (high byte) iph 218 dah x x x x x x x x instruction pointer (low byte) ipl 219 dbh x x x x x x x x interrupt request register irq 220 dch 0 0 0 0 0 0 0 0 interrupt mask register imr 221 ddh x x x x x x x x system mode register sym 222 deh 0 ? ? x x x 0 0 register page pointer pp 223 dfh 0 0 0 0 0 0 0 0 s3c84bb/f84bb reset and power-down 8-3 table 8-2. s3c84bb/f84bb set 1, bank 0 register values after reset address bit values after reset register name mnemonic dec hex 7 6 5 4 3 2 1 0 port 0 data register p0 224 e0h 0 0 0 0 0 0 0 0 port 1 data register p1 225 e1h 0 0 0 0 0 0 0 0 port 2 data register p2 226 e2h 0 0 0 0 0 0 0 0 port 3 data register p3 227 e3h 0 0 0 0 0 0 0 0 port 4 data register p4 228 e4h 0 0 0 0 0 0 0 0 port 5 data register p5 229 e5h 0 0 0 0 0 0 0 0 port 6 data register p6 230 e6h 0 0 0 0 0 0 0 0 port 7 data register p7 231 e7h 0 0 0 0 0 0 0 0 port 8 data register p8 232 e8h 0 0 0 0 0 0 0 0 timer a/1 interrupt pending register tintpnd 233 e9h ? ? 0 0 0 0 0 0 timer a control register tacon 234 eah 0 0 0 0 0 0 0 ? timer a data register tadata 235 ebh 1 1 1 1 1 1 1 1 timer a counter register tacnt 236 ech 0 0 0 0 0 0 0 0 port 8 control register (high byte) p8conh 237 edh 1 1 1 1 0 0 0 0 port 8 control register (low byte) p8conl 238 eeh 0 0 0 0 0 0 0 0 port 8 interrupt/pending register p8intpnd 239 efh 1 1 0 0 1 1 0 0 port 0 control register p0con 240 f0h 0 0 0 0 0 0 0 0 port 1 control register p1con 241 f1h 0 0 0 0 0 0 0 0 port 2 control register (high byte) p2conh 242 f2h 0 0 0 0 0 0 0 0 port 2 control register (low byte) p2conl 243 f3h 0 0 0 0 0 0 0 0 port 3 control register (high byte) p3conh 244 f4h 0 0 0 0 0 0 0 0 port 3 control register (low byte) p3conl 245 f5h 0 0 0 0 0 0 0 0 port 4 control register (high byte) p4conh 246 f6h 0 0 0 0 0 0 0 0 port 4 control register (low byte) p4conl 247 f7h 0 0 0 0 0 0 0 0 port 5 control register (high byte) p5conh 248 f8h 0 0 0 0 0 0 0 0 port 5 control register (low byte) p5conl 249 f9h 0 0 0 0 0 0 0 0 port 4 interrupt control register p4int 250 fah 0 0 0 0 0 0 0 0 port 4 interrupt/pending register p4intpnd 251 fbh 0 0 0 0 0 0 0 0 location fch is factory use only basic timer counter register btcnt 253 fdh 0 0 0 0 0 0 0 0 location feh is not mapped interrupt priority register ipr 255 ffh x x x x x x x x reset and power-down s3c84bb/f84bb 8-4 table 8-3. s3c84bb/f84bb set 1, bank 1 register values after reset address bit values after reset register name mnemonic dec hex 7 6 5 4 3 2 1 0 sio data register siodata 224 e0h 0 0 0 0 0 0 0 0 sio control register siocon 225 e1h 0 0 0 0 0 0 0 0 uart0 data register udata0 226 e2h 1 1 1 1 1 1 1 1 uart0 control register uartcon0 227 e3h 0 0 0 0 0 0 0 0 uart0 baud rate data register brdata0 228 e4h 1 1 1 1 1 1 1 1 uart0,1 pending register uartpnd 229 e5h - - - - 0 0 0 0 timer 1(0) data register (high byte) t1datah0 230 e6h 1 1 1 1 1 1 1 1 timer 1(0) data register (low byte) t1datal0 231 e7h 1 1 1 1 1 1 1 1 timer 1(1) data register (high byte) t1datah1 232 e8h 1 1 1 1 1 1 1 1 timer 1(1) data register (low byte) t1datal1 233 e9h 1 1 1 1 1 1 1 1 timer 1(0) control register t1con0 234 eah 0 0 0 0 0 0 0 0 timer 1(1) control register t1con1 235 ebh 0 0 0 0 0 0 0 0 timer 1(0) counter register(high byte) t1cnth0 236 ech 0 0 0 0 0 0 0 0 timer 1(0) counter register(low byte) t1cntl0 237 edh 0 0 0 0 0 0 0 0 timer 1(1) counter register(high byte) t1cnth1 238 eeh 0 0 0 0 0 0 0 0 timer 1(1) counter register(low byte) t1cntl1 239 efh 0 0 0 0 0 0 0 0 timer c(0) data register tcdata0 240 f0h 1 1 1 1 1 1 1 1 timer c(1) data register tcdata1 241 f1h 1 1 1 1 1 1 1 1 timer c(0) control register tccon0 242 f2h 0 0 0 0 0 0 0 0 timer c(1) control register tccon1 243 f3h 0 0 0 0 0 0 0 0 sio prescaler control register siops 244 f4h 0 0 0 0 0 0 0 0 port 7 control register p7con 245 f5h 0 0 0 0 0 0 0 0 d/a converter data register dadata 246 f6h 0 0 0 0 0 0 0 0 a/d, d/a converter control register adacon 247 f7h 0 0 0 0 0 0 0 0 a/d converter data register(high byte) addatah 248 f8h 0 0 0 0 0 0 0 0 a/d converter data register(low byte) addatal 249 f9h 0 0 0 0 0 0 0 0 uart1 data register udata1 250 fah 1 1 1 1 1 1 1 1 uart1 control register uartcon1 251 fbh 0 0 0 0 0 0 0 0 uart1 baud rate data register brdata1 252 fch 1 1 1 1 1 1 1 1 flash memory control register fmcon 253 fdh 0 0 0 0 0 0 0 0 pattern generation control register pgcon 254 feh ? ? ? ? 0 0 0 0 pattern generation data register pgdata 255 ffh 0 0 0 0 0 0 0 0 s3c84bb/f84bb reset and power-down 8-5 power-down modes stop mode stop mode is invoked by the instruction stop (opcode 7fh). in stop mode, the operation of the cpu and all peripherals is halted. that is, the on-chip main oscillator stops and the supply current is reduced to less than 3 a. all system functions stop when the clock "freezes," but data stored in the internal register file is retained. stop mode can be released in one of two ways: by a reset or by interrupts. note do not use stop mode if you are using an external clock source because x in input must be restricted internally to v ss to reduce current leakage. using reset to release stop mode stop mode is released when the reset signal is released and returns to high level: all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained. a reset operation automatically selects a slow clock (1/16) because clkcon.3 and clkcon.4 are cleared to '00b'. after the programmed oscillation stabilization interval has elapsed, the cpu starts the system initialization routine by fetching the program instruction stored in rom location 0100h (and 0101h). using an external interrupt to release stop mode external interrupts with an rc-delay noise filter circuit can be used to release stop mode. which interrupt you can use to release stop mode in a given situation depends on the microcontroller's current internal operating mode. the external interrupts in the s3f84bb interrupt structure that can be used to release stop mode are: ? external interrupts p4.0/int0-p4.7/int7, p8.4/int8 and p8.5/int9 please note the following conditions for stop mode release: ? if you release stop mode using an external interrupt, the current values in system and peripheral control registers are unchanged. ? if you use an external interrupt for stop mode release, you can also program the duration of the oscillation stabilization interval. to do this, you must make the appropriate control and clock settings before entering stop mode. ? when the stop mode is released by external interrupt, the clkcon.4 and clkcon.3 bit-pair setting remains unchanged and the currently selected clock value is used. ? the external interrupt is serviced when the stop mode release occurs. following the iret from the service routine, the instruction immediately following the one that initiated stop mode is executed. using an internal interrupt to release stop mode activate any enabled interrupt, causing stop mode to be released. other things are same as using external interrupt. reset and power-down s3c84bb/f84bb 8-6 idle mode idle mode is invoked by the instruction idle (opcode 6fh). in idle mode, cpu operations are halted while some peripherals remain active. during idle mode, the internal clock signal is gated away from the cpu, but all peripherals timers remain active. port pins retain the mode (input or output) they had at the time idle mode was entered. there are two ways to release idle mode: 1. execute a reset. all system and peripheral control registers are reset to their default values and the contents of all data registers are retained. the reset automatically selects the slow clock fxx/16 because clkcon.4 and clkcon.3 are cleared to ?00b?. if interrupts are masked, a reset is the only way to release idle mode. 2. activate any enabled interrupt, causing idle mode to be released. when you use an interrupt to release idle mode, the clkcon.4 and clkcon.3 register values remain unchanged, and the currently selected clock value is used. the interrupt is then serviced. when the return-from-interrupt (iret) occurs, the instruction immediately following the one that initiated idle mode is executed. s3c84bb/f84bb i/o ports 9-1 i/o ports overview the s3c84bb/f84bb microcontroller has nine bit-programmable i/o ports, p0-p8. the port 8 are 6-bit ports and the others are 8-bit ports. this gives a total of 70 i/o pins. each port can be flexibly configured to meet application design requirements. the cpu accesses ports by directly writing or reading port registers. no special i/o instructions are required. table 9-1 gives you a general overview of the s3c84bb/f84bb i/o port functions. table 9-1. s3c84bb/f84bb port configuration overview port configuration options 0 bit programmable port; input or output mode selected by software; input or push-pull output. software assignable pull-up. alternately, p0.0-p0.7 can be used as the pg output port (pg0-pg7). 1 bit programmable port; input or output mode selected by software; input or push-pull output. software assignable pull-up. 2 bit programmable port; input or output mode selected by software; input or push-pull output. software assignable pull-up. alternately, p2.0~p2.7 can be used as i/o for timera, timerb, dac, sio 3 bit programmable port; input or output mode selected by software; input or push-pull output. software assignable pull-up. alternately, p3.0~p3.7 can be used as i/o for timerc0/c1, timer10/11 4 bit programmable port; input or output mode selected by software; input or push-pull output. software assignable pull-up. p4.0-p4.7 can alternately be used as inputs for external interrupts int0-int7, respectively (with noise filters and interrupt controller) 5 bit programmable port; input or output mode selected by software; input or push-pull output. software assignable pull-up. alternately, p5.0~p5.3 can be used as i/o for serial port uart0, uart1, respectively. 6 n-channel, open-drain output only port. 7 general-purpose digital input ports. alternatively used as analog input pins for a/d converter modules. 8 bit programmable port; input or output mode selected by software; input or push-pull output. software assignable pull-up. p8.4, p8.5 can alternately be used as inputs for external interrupts int8, int9, respectively (with noise filters and interrupt controller) i/o ports s3c84bb/f84bb 9-2 port data registers table 9-2 gives you an overview of the register locations of all five s3c84bb/f84bb i/o port data registers. data registers for ports 0, 1, 2, 3, 4, 5, 6, 7 and 8 have the general format shown in table 9-2. table 9-2. port data register summary register name mnemonic decimal hex location r/w port 0 data register p0 224 e0h set 1, bank 0 r/w port 1 data register p1 225 e1h set 1, bank 0 r/w port 2 data register p2 226 e2h set 1, bank 0 r/w port 3 data register p3 227 e3h set 1, bank 0 r/w port 4 data register p4 228 e4h set 1, bank 0 r/w port 5 data register p5 229 e5h set 1, bank 0 r/w port 6 data register p6 230 e6h set 1, bank 0 r/w port 7 data register p7 231 e7h set 1, bank 0 r/w port 8 data register p8 232 e8h set 1, bank 0 r/w s3c84bb/f84bb i/o ports 9-3 port 0 port 0 is an 8-bit i/o port that you can use two ways: ? general-purpose i/o ? alternative function: pgout7-pgout0 port 0 is accessed directly by writing or reading the port 0 data register, p0 at location e0h in set 1, bank 0. port 0 control register (p0con) port 0 pins are configured individually by bit-pair settings in one control registers located in set 1, bank 0: p0con (f0h). when programming the port, please remember that any alternative peripheral i/o function you configure using the port 0 control registers must also be enabled in the associated peripheral module. i/o ports s3c84bb/f84bb 9-4 port 0 control register (p0con) f0h, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 p0.7/p0.6/ p0.5/p0.4/ pgout[7:4] p0.3/p0.2/ pgout[3:2] p0.1/ pgout[1] p0.0/ pgout[0] .7 .6 bit/p0.7/p0.6/p0.5/p0.4 00 01 10 11 input mode input mode, pull-up push-pull output alternative function mode(pgout[7:4]) .5 .4 bit/p0.3/p0.2 00 01 10 11 .3 .2 bit/p0.1 00 01 10 11 .1 .0 bit/p0.0 00 01 10 11 input mode input mode, pull-up push-pull output alternative function mode(pgout[3:2]) input mode input mode, pull-up push-pull output alternative function mode(pgout[1]) input mode input mode, pull-up push-pull output alternative function mode(pgout[0]) figure 9-1. port 0 control register (p0con) s3c84bb/f84bb i/o ports 9-5 port 1 port 1 is an 8-bit i/o port that you can use one ways: ? general-purpose i/o port 1 is accessed directly by writing or reading the port 1 data register, p1 at location e1h in set 1, bank 0. port 1 control register (p1con) port 1 pins are configured individually by bit-pair settings in one control registers located in set 1, bank 0: p1con (f1h). when programming the port, please remember that any alternative peripheral i/o function you configure using the port 1 control registers must also be enabled in the associated peripheral module. i/o ports s3c84bb/f84bb 9-6 port 1 control register (p1con) f1h, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 p1.7/p1.6 p1.5/p1.4 p1.3/p1.2 p1.0/p1.0 .7 .6 bit/p1.7/p1.6 00 01 1x input mode input mode, pull-up push-pull output .5 .4 bit/p1.5/p1.4 .3 .2 bit/p1.3/p1.2 .1 .0 bit/p1.1//p.0 input mode input mode, pull-up push-pull output input mode input mode, pull-up push-pull output input mode input mode, pull-up push-pull output 00 01 1x 00 01 1x 00 01 1x figure 9-2. port 1 control register (p1con) s3c84bb/f84bb i/o ports 9-7 port 2 port 2 is an 8-bit i/o port with individually configurable pins. port 2 pins are accessed directly by writing or reading the port 2 data register, p2 at location e2h in set 1, bank 0. p2.0?p2.7 can serve as inputs, outputs (push pull) or you can configure the following alternative functions: ? low-byte pins (p2.0-p2.3): daout, sck, si, so ? high-byte pins (p2.4-p2.7): taout, tacap, tack, tbpwm port 2 control register (p2conh, p2conl) port 2 has two 8-bit control registers: p2conh for p2.4?p2.7 and p2conl for p2.0?p2.3. a reset clears the p2conh and p2conl registers to ?00h?, configuring all pins to input mode. you use control registers settings to select input or output mode (push-pull) and enable the alternative functions. when programming the port, please remember that any alternative peripheral i/o function you configure using the port 2 control registers must also be enabled in the associated peripheral module. i/o ports s3c84bb/f84bb 9-8 port 2 control register, high byte (p2conh) f2h, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 p2.4/tbpwm .7 .6 bit/p2.7/taout 00 01 10 11 input mode input mode, pull-up push-pull output alternative output mode(taout) .5 .4 bit/p2.6/tacap 00 01 10 11 .3 .2 bit/p2.5/tack 00 01 10 11 .1 .0 bit/p2.4/tbpwm 00 01 10 11 p2.5/tack p2.6/tacap p2.7/taout note: when use this port 2, user must be care of the pull-up resistance status. input mode(tacap) input mode, pull-up(tacap) push-pull output alternative output mode(not used) input mode(tack) input mode, pull-up(tack) push-pull output alternative output mode(not used) input mode input mode, pull-up push-pull output alternative output mode(tbpwm) figure 9-3. port 2 high-byte control register (p2conh) s3c84bb/f84bb i/o ports 9-9 port 2 control register, low byte (p2conl) f3h, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 p2.0/so .7 .6 bit/p2.3/daout 00 01 10 11 input mode input mode, pull-up push-pull output alternative output mode(daout) .5 .4 bit/p2.2/sck 00 01 10 11 .3 .2 bit/p2.1/si 00 01 10 11 .1 .0 bit/p2.0/so 00 01 10 11 p2.1/si p2.2/sck p2.3/ daout note: when use this port 2, user must be care of the pull-up resistance status. input mode(sck input) input mode, pull-up(sck input) push-pull output alternative output mode(sck output) input mode(si) input mode, pull-up(si) push-pull output alternative output mode(not used) input mode input mode, pull-up push-pull output alternative output mode(so) figure 9-4. port 2 low-byte control register (p2conl) i/o ports s3c84bb/f84bb 9-10 port 3 port 3 is an 8-bit i/o port that can be used for general-purpose i/o. the pins are accessed directly by writing or reading the port 3 data register, p3 at location e3h in set 1, bank 0. p3.7?p3.0 can serve as inputs, outputs (push pull) or you can configure the following alternative functions: ? low-byte pins (p3.0-p3.3): t1cap1, t1cap0, t1ck1, t1ck0 ? high-byte pins (p3.4-p3.7): tcout1, tcout0, t1out1, t1out0 to individually configure the port 3 pins p3.0?p3.7, you make bit-pair settings in two control registers located in set 1, bank 0: p3conl (low byte, f5h) and p3conh (high byte, f4h). port 3 control registers (p3conh, p3conl) two 8-bit control registers are used to configure port 3 pins: p3conl (f5h, set 1, bank 0) for pins p3.0?p3.3 and p3conh (f4h, set 1, bank 0) for pins p3.4?p3.7. each byte contains four bit-pairs and each bit-pair configures one pin of port 3. s3c84bb/f84bb i/o ports 9-11 port 3 control register, high byte (p3conh) f4h, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 p3.4/t1out0 .7 .6 bit : p3.7/tcout1 00 01 10 11 input mode input mode, pull-up push-pull output alternative function(tcout1) .5 .4 bit : p3.6/tcout0 00 01 10 11 .3 .2 bit : p3.5/t1out1 00 01 10 11 .1 .0 bit : p3.4/t1out0 00 01 10 11 p3.5/t1out1 p3.6/tcout0 p3.7/tcout1 input mode input mode, pull-up push-pull output alternative function(tcout0) input mode input mode, pull-up push-pull outputt alternative function(t1out1) input mode input mode, pull-up push-pull outputt alternative function(t1out0) figure 9-5. port 3 high-byte control register (p3conh) i/o ports s3c84bb/f84bb 9-12 port 3 control register, low byte (p3conl) f5h, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 p3.0/t1ck0 .7 .6 bit/p3.3/t1cap1 00 01 1x input mode(t1cap1) input mode, pull-up(t1cap1) push-pull output .5 .4 bit/p3.2/t1cap0 .3 .2 bit/p3.1/t1ck1 .1 .0 bit/p3.0/t1ck0 p3.1/t1ck1 p3.2/t1cap0 p3.3/t1cap1 00 01 1x input mode(t1cap0) input mode, pull-up(t1cap0) push-pull output 00 01 1x input mode(t1ck1) input mode, pull-up(t1ck1) push-pull output 00 01 1x input mode(t1ck0) input mode, pull-up(t1ck0) push-pull output figure 9-6. port 3 low-byte control register (p3conl) s3c84bb/f84bb i/o ports 9-13 port 4 port 4 is an 8-bit i/o port that you can use two ways: ? general-purpose i/o ? external interrupt inputs for int0-int7 port 4 is accessed directly by writing or reading the port 4 data register, p4 at location e4h in set 1, bank 0. port 4 control register (p4conh, p4conl) port 4 pins are configured individually by bit-pair settings in two control registers located in set 1, bank 0: p4conl (low byte, f7h) and p4conh (high byte, f6h). when you select output mode, a push-pull circuit is configured. in input mode, three different selections are available: ? schmitt trigger input with interrupt generation on falling signal edges. ? schmitt trigger input with interrupt generation on rising signal edges. ? schmitt trigger input with pull-up resistor and interrupt generation on falling signal edges. port 4 interrupt enable and pending registers (p4int, p4intpnd) to process external interrupts at the port 4 pins, two additional control registers are provided: the port 4 interrupt enable register p4int (fah, set 1, bank 0) and the port 4 interrupt pending register p4intpnd (fbh, set 1, bank 0). the port 4 interrupt pending register p4intpnd lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. the application program detects interrupt requests by polling the p4intpnd register at regular intervals. when the interrupt enable bit of any port 4 pin is ?1?, a rising or falling signal edge at that pin will generate an interrupt request. the corresponding p4intpnd bit is then automatically set to ?1? and the irq level goes low to signal the cpu that an interrupt request is waiting. when the cpu acknowledges the interrupt request, application software must clear the pending condition by writing a ?0? to the corresponding p4intpnd bit. i/o ports s3c84bb/f84bb 9-14 port 4 control register, high byte (p4conh) f6h, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 p4.7/ int7 p4.6/ int6 p4.5/ int5 p4.4/ int4 .7 .6 bit/p4.7int7 00 01 10 11 input mode; (falling edge interrupt) input mode; (rising edge interrupt) input mode, pull-up; (falling edge interrupt) push-pull output .5 .4 bit/p4.6/int6 00 01 10 11 .3 .2 bit/p4.5/int5 00 01 10 11 .1 .0 bit/p4.4/int4 00 01 10 11 input mode; (falling edge interrupt) input mode; (rising edge interrupt) input mode, pull-up; (falling edge interrupt) push-pull output input mode; (falling edge interrupt) input mode; (rising edge interrupt) input mode, pull-up; (falling edge interrupt) push-pull output input mode; (falling edge interrupt) input mode; (rising edge interrupt) input mode, pull-up; (falling edge interrupt) push-pull output figure 9-7. port 4 high-byte control register (p4conh) s3c84bb/f84bb i/o ports 9-15 port 4 control register, low byte (p4conl) f7h, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 p4.3/ int3 p4.2/ int2 p4.1/ int1 p4.0/ int0 .7 .6 bit/p4.3/int3 00 01 10 11 input mode; (falling edge interrupt) input mode; (rising edge interrupt) input mode, pull-up; (falling edge interrupt) push-pull output .5 .4 bit/p4.2/int2 00 01 10 11 .3 .2 bit/p4.1/int1 00 01 10 11 .1 .0 bit/p4.0/int0 00 01 10 11 input mode; (falling edge interrupt) input mode; (rising edge interrupt) input mode, pull-up; (falling edge interrupt) push-pull output input mode; (falling edge interrupt) input mode; (rising edge interrupt) input mode, pull-up; (falling edge interrupt) push-pull output input mode; (falling edge interrupt) input mode; (rising edge interrupt) input mode, pull-up; (falling edge interrupt) push-pull output figure 9-8. port 4 low-byte control register (p4conl) i/o ports s3c84bb/f84bb 9-16 port 4 interrupt control register (p4int) fah, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 int7 p4int bit configuration settings: 0 1 interrupt disable interrupt enable int6 int5 int4 int3 int2 int1 int0 figure 9-9. port 4 interrupt control register (p4int) port 4 interrupt pending register (p4intpnd) fbh, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 pnd7 p4intpnd bit configuration settings: 0 1 interrupt request is not pending, pending bit clear when write 0 interrupt request is pending pnd6 pnd5 pnd4 pnd3 pnd2 pnd1 pnd0 figure 9-10. port 4 interrupt pending register (p4intpnd) s3c84bb/f84bb i/o ports 9-17 port 5 port 5 is an 8-bit i/o port with individually configurable pins. port 5 pins are accessed directly by writing or reading the port 5 data register, p5 at location e5h in set 1, bank 0. p5.7?p5.4 can serve as inputs, outputs (push pull or open-drain). p5.3?p5.0 can serve as inputs, outputs (push pull) or you can configure the following alternative functions: ? low-byte pins (p5.3-p5.0): rxd0, txd0, rxd1, txd1 port 5 control register (p5conh, p5conl) port 5 has two 8-bit control registers: p5conh for p5.4?p5.7 and p5conl for p5.0?p5.3. a reset clears the p5conh and p5conl registers to ?00h?, configuring all pins to input mode. you use control registers settings to select input or output mode (push-pull, open-drain) and enable the alternative functions. when programming the port, please remember that any alternative peripheral i/o function you configure using the port 5 control registers must also be enabled in the associated peripheral module. i/o ports s3c84bb/f84bb 9-18 port 5 control register, high byte (p5conh) f8h, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 p5.4 .7 .6 bit : p5.7 00 01 10 11 input mode input mode, pull-up push-pull output open-drain mode .5 .4 bit : p5.6 00 01 10 11 .3 .2 bit : p5.5 00 01 10 11 .1 .0 bit : p5.4 00 01 10 11 p5.5 p5.6 p5.7 input mode input mode, pull-up push-pull output open-drain mode input mode input mode, pull-up push-pull output open-drain mode input mode input mode, pull-up push-pull output open-drain mode figure 9-11. port 5 high-byte control register (p5conh) s3c84bb/f84bb i/o ports 9-19 port 5 control register, low byte (p5conl) f9h, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 p5.0/ txd1 .7 .6 bit/p5.3/rxd0 00 01 10 11 input mode(rxd0 input) input mode, pull-up(rxd0 input) push-pull output alternative output mode(rxd0 output) .5 .4 bit/p5.2/txd0 00 01 10 11 .3 .2 bit/p5.1/rxd1 00 01 10 11 .1 .0 bit/p5.0/txd1 00 01 10 11 p5.1/ rxd1 p5.2/ txd0 p5.3/ rxd0 input mode input mode, pull-up push-pull output alternative output mode(txd0 output) input mode(rxd1 input) input mode, pull-up(rxd1 input) push-pull output alternative output mode(rxd1 output) input mode input mode, pull-up push-pull output alternative output mode(txd1 output) figure 9-12. port 5 low-byte control register (p5conl) i/o ports s3c84bb/f84bb 9-20 port 6 port 6 is an 8-bit open drain output only port pins. port 6 pins are accessed directly by writing the port6 data register, p6 at location e6h in set 1, bank 0. s3c84bb/f84bb i/o ports 9-21 port 7 port 7 is an 8-bit input port that you can use two ways: ? general-purpose input ? alternative function: adc0-adc7 input port 7 is accessed directly by reading the port 7 data register, p7 at location e7h in set 1, bank 0. port 7 control register (p7con) port 7 pins are configured individually by bit-pair settings in one control registers located in set 1, bank 1: p7con (f5h). when programming the port, please remember that any alternative peripheral i function you configure using the port 7 control registers must also be enabled in the associated peripheral module. i/o ports s3c84bb/f84bb 9-22 port 7 control register (p7con) f5h, set 1, bank 1, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 p7.7/ adc7 .7 bit : p7.7/adc7 0 1 input mode adc input mode p7.6/ adc6 p7.5/ adc5 p7.4/ adc4 p7.3/ adc3 p7.2/ adc2 p7.1/ adc1 p7.0/ adc0 .6 bit : p7.6/adc6 0 1 input mode adc input mode .5 bit : p7.5/adc5 0 1 input mode adc input mode .4 bit : p7.4/adc4 0 1 input mode adc input mode .3 bit : p7.3/adc3 0 1 input mode adc input mode .2 bit : p7.2/adc2 0 1 input mode adc input mode .1 bit : p7.1/adc1 0 1 input mode adc input mode .0 bit : p7.0/adc0 0 1 input mode adc input mode figure 9-13. port 7 control register (p7con) s3c84bb/f84bb i/o ports 9-23 port 8 port 8 is an 8-bit i/o port that you can use two ways: ? general-purpose i/o ? external interrupt inputs for int8-int9 port 8 is accessed directly by writing or reading the port 8 data register, p8 at location e8h in set 1, bank 0. port 8 control register (p8conh, p8conl) port 8 pins are configured individually by bit-pair settings in two control registers located in set 1, bank 0: p8conl (low byte, eeh) and p8conh (high byte, edh). when you select output mode, a push-pull circuit is configured. in input mode, three different selections are available: ? schmitt trigger input with interrupt generation on falling signal edges. ? schmitt trigger input with interrupt generation on rising signal edges. ? schmitt trigger input with pull-up resistor and interrupt generation on falling signal edges. port 8 interrupt enable and pending registers (p8intpnd) to process external interrupts at the port 8 pins, one additional control register is provided: the port 8 interrupt enable register p8intpnd (efh, set 1, bank 0). the port 8 interrupt pending register p8intpnd lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. the application program detects interrupt requests by polling the p8intpnd register at regular intervals. when the interrupt enable bit of any port 8 pin is ?1?, a rising or falling signal edge at that pin will generate an interrupt request. the corresponding p8intpnd bit is then automatically set to ?1? and the irq level goes low to signal the cpu that an interrupt request is waiting. when the cpu acknowledges the interrupt request, application software must the clear the pending condition by writing a ?0? to the corresponding p8intpnd bit. i/o ports s3c84bb/f84bb 9-24 port 8 control register, high byte (p8conh) edh, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 not used p8.5/ int9 p8.4/ int8 .3 .2 bit : p8.5/int9 00 01 10 11 .1 .0 bit : p8.4/int8 00 01 10 11 input mode; (falling edge interrupt) input mode; (rising edge interrupt) input mode, pull-up; (falling edge interrupt) push-pull output input mode; (falling edge interrupt) input mode; (rising edge interrupt) input mode, pull-up; (falling edge interrupt) push-pull output figure 9-14. port 8 high-byte control register (p8conh) s3c84bb/f84bb i/o ports 9-25 port 8 control register, low byte (p8conl) eeh, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 p8.3 p8.2 p8.1 p8.0 .7 .6 bit : p8.3 00 01 1x input mode input mode, pull-up push-pull output .5 .4 bit : p8.2 .3 .2 bit : p8.1 .1 .0 bit : p8.0 00 01 1x input mode input mode, pull-up push-pull output 00 01 1x input mode input mode, pull-up push-pull output 00 01 1x input mode input mode, pull-up push-pull output figure 9-15. port 8 low-byte control register (p8conl) i/o ports s3c84bb/f84bb 9-26 interrupt request is not pending, pending bit clear when write 0 interrupt request is not pending, pending bit clear when write 0 port 8 interrupt pending register (p8intpnd) efh, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 .5 bit : p8.5/pnd9 0 1 interrupt request is pending not used p8.5/ pnd9 p8.4/ pnd8 not used p8.5/ int9 p8.4/ int8 .4 bit : p8.4/pnd8 0 1 interrupt request is pending .1 bit : p8.5/int9 0 1 disable interrupt enable interrupt .0 bit : p8.4/int8 0 1 disable interrupt enable interrupt figure 9-16. port 8 interrupt pending register (p8intpnd) s3c84bb/f84bb basic timer 10-1 basic timer overview basic timer (bt) you can use the basic timer (bt) in two different ways: ? as a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. ? to signal the end of the required oscillation stabilization interval after a reset or a stop mode release. the functional components of the basic timer block are: ? clock frequency divider (fxx divided by 4096, 1024 or 128) with multiplexer ? 8-bit basic timer counter, btcnt (set 1, bank 0, fdh, read-only) ? basic timer control register, btcon (set 1, d3h, read/write) basic timer control register (btcon) the basic timer control register, btcon, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. it is located in set 1, address d3h, and is read/write addressable using register addressing mode. a reset clears btcon to '00h'. this enables the watchdog function and selects a basic timer clock frequency of f xx /4096. to disable the watchdog function, write the signature code '1010b' to the basic timer register control bits btcon.7?btcon.4. the 8-bit basic timer counter, btcnt (set 1, bank 0, fdh), can be cleared at any time during normal operation by writing a "1" to btcon.1. to clear the frequency dividers, write a "1" to btcon.0. basic timer s3c84bb/f84bb 10-2 basic timer control register (btcon) d3h, set 1, r/w lsb msb.7.6.5.4.3.2.1.0 divider clear bit: 0 = no effect 1 = clear divider basic timer counter clear bit: 0 = no effect 1 = clear btcnt basic timer input clock selection bit: 00 = fxx/4096 01 = fxx/1024 10 = fxx/128 11 = fxx/16 (not used) watchdog timer enable bit: 1010b = disable watchdog function other value = enable watchdog function figure 10-1. basic timer control register (btcon) s3c84bb/f84bb basic timer 10-3 basic timer function description watchdog timer function you can program the basic timer overflow signal (btovf) to generate a reset by setting btcon.7?btcon.4 to any value other than "1010b". (the "1010b" value disables the watchdog function.) a reset clears btcon to "00h", automatically enabling the watchdog timer function. a reset also selects the cpu clock (as determined by the current clkcon register setting), divided by 4096, as the bt clock. the mcu is reset whenever a basic timer counter overflow occurs, during normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occurring, to do this, the btcnt value must be cleared (by writing a ?1? to btcon.1) at regular intervals. if a system malfunction occurs due to circuit noise or some other error condition, the bt counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. in other words, during the normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, btcnt) is always broken by a btcnt clear instruction. if a malfunction does occur, a reset is triggered automatically. oscillation stabilization interval timer function you can also use the basic timer to program a specific oscillation stabilization interval following a reset or when stop mode has been released by an external interrupt. in stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. the btcnt value then starts increasing at the rate of fxx/4096 (for reset), or at the rate of the preset clock source (for an external interrupt). when btcnt.4 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the cpu so that it can resume normal operation. in summary, the following events occur when stop mode is released: 1. during stop mode, a power-on reset or an interrupt occurs to trigger the stop mode release and oscillation starts. 2. if a power-on reset occurred, the basic timer counter will increase at the rate of fxx/4096. if an interrupt is used to release stop mode, the btcnt value increases at the rate of the preset clock source. 3. clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter overflows. 4. when a btcnt.4 overflow occurs, normal cpu operation resumes. basic timer s3c84bb/f84bb 10-4 note: during a power-on reset operation, the cpu is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows). mux fxx/4096 div fxx/1024 fxx/128 fxx bits 3, 2 bit 0 basic timer control register (write '1010xxxxb' to disable) clear bit 1 reset or stop data bus 8-bit up counter (btcnt, read-only) start the cpu (note) ovf reset r figure 10-2. basic timer block diagram s3c84bb/f84bb 8-bit timer a/b/c(0/1) 11-1 8-bit timer a/b/c(0/1) 8-bit timer a overview the 8-bit timer a is an 8-bit general-purpose timer/counter. timer a has three operating modes, you can select one of them using the appropriate tacon setting: ? interval timer mode (toggle output at taout pin) ? capture input mode with a rising or falling edge trigger at the tacap pin ? pwm mode (tapwm); pwm output shares its output port with taout pin timer a has the following functional components: ? clock frequency divider (fxx divided by 1024, 256, or 64) with multiplexer ? external clock input pin (tack) ? 8-bit counter (tacnt), 8-bit comparator, and 8-bit reference data register (tadata) ? i/o pins for capture input (tacap) or pwm or match output (tapwm, taout) ? timer a overflow interrupt (irq0, vector bah) and match/capture interrupt (irq0, vector b8h) generation ? timer a control register, tacon (set 1, bank0, eah, read/write) 8-bit timer a/b/c(0/1) s3c84bb/f84bb 11-2 function description timer a interrupts (irq0, vectors b8h and bah) the timer a module can generate two interrupts: the timer a overflow interrupt (taovf), and the timer a match/ capture interrupt (taint). taovf is interrupt level irq0, vector bah. taint also belongs to interrupt level irq0, but is assigned the separate vector address, b8h. a timer a overflow interrupt pending condition is automatically cleared by hardware when it has been serviced. a timer a match/capture interrupt, taint pending condition is also cleared by hardware when it has been serviced. interval timer function the timer a module can generate an interrupt: the timer a match interrupt (taint). taint belongs to interrupt level irq0, and is assigned the separate vector address, b8h. when timer a match interrupt occurs and is serviced by the cpu, the pending condition is cleared automatically by hardware. in interval timer mode, a match signal is generated and taout is toggled when the counter value is identical to the value written to the ta reference data register, tadata. the match signal generates a timer a match interrupt (taint, vector b8h) and clears the counter. if, for example, you write the value 10h to tadata and 0ah to tacon, the counter will increment until it reaches 10h. at this point, the ta interrupt request is generated, the counter value is reset, and counting resumes. pulse width modulation mode pulse width modulation (pwm) mode lets you program the width (duration) of the pulse that is output at the tapwm pin. as in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer a data register. in pwm mode, however, the match signal does not clear the counter. instead, it runs continuously, overflowing at ffh, and then continues incrementing from 00h. although timer a overflow interrupt is occurred, this interrupt is not typically used in pwm-type applications. instead, the pulse at the tapwm pin is held to low level as long as the reference data value is less than or equal to ( ) the counter value and then the pulse is held to high level for as long as the data value is greater than ( > ) the counter value. one pulse width is equal to t clk 256 . capture mode in capture mode, a signal edge that is detected at the tacap pin opens a gate and loads the current counter value into the ta data register. you can select rising or falling edges to trigger this operation. timer a also gives you capture input source: the signal edge at the tacap pin. you select the capture input by setting the value of the timer a capture input selection bit in the port 2 control register, p2conh, (set 1, bank 0, f2h). when p2conh.5.4 is 00, the tacap input or normal input is selected. when p2conh.5.4 is set to 10, normal output is selected. both kinds of timer a interrupts can be used in capture mode: the timer a overflow interrupt is generated whenever a counter overflow occurs; the timer a match/capture interrupt is generated whenever the counter value is loaded into the ta data register. by reading the captured data value in tadata, and assuming a specific value for the timer a clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the tacap pin. s3c84bb/f84bb 8-bit timer a/b/c(0/1) 11-3 timer a control register (tacon) you use the timer a control register, tacon, to ? select the timer a operating mode (interval timer, capture mode, or pwm mode) ? select the timer a input clock frequency ? clear the timer a counter, tacnt ? enable the timer a overflow interrupt or timer a match/capture interrupt ? clear timer a match/capture interrupt pending conditions tacon is located in set 1, bank 0 at address eah, and is read/write addressable using register addressing mode. a reset clears tacon to '00h'. this sets timer a to normal interval timer mode, selects an input clock frequency of fxx/1024, and disables all timer a interrupts. you can clear the timer a counter at any time during normal operation by writing a "1" to tacon.3. the timer a overflow interrupt (taovf) is interrupt level irq0 and has the vector address bah. when a timer a overflow interrupt occurs and is serviced by the cpu, the pending condition is cleared automatically by hardware. to enable the timer a match/capture interrupt (irq0, vector b8h), you must write tacon.1 to "1". to generate the exact time interval, you should write ?1? to tacon.3 and ?0? to tintpnd.0, which cleared counter and interrupt pending bit . timer a control register (tacon) eah, set 1, bank 0, r/w, reset: 00h lsb msb .7 .6 .5 .4 .3 .2 .1 .0 timer a match/capture interrupt enable bit: 0 = disable interrupt 1 = enable interrrupt timer a input clock selection bit: 00 = fxx/1024 01 = fxx/256 10 = fxx/64 11 = external clock (tack) timer a operating mode selection bit: 00 = interval mode (taout mode) 01 = capture mode (capture on rising edge, counter running, ovf can occur) 10 = capture mode (capture on falling edge, counter running, ovf can occur) 11 = pwm mode (ovf interrupt and match interrupt can occur) not used timer a overflow interrupt enable bit: 0 = disable overflow interrupt 1 = enable overflow interrrupt timer a counter clear bit: 0 = no effect 1 = clear the timer a counter ( when write ) note: when the counter clear bit(.3) is set, the 8-bit counter is cleared and it also is cleared automatically. pending bit of overflow and match/capture intterupt are located in tintpnd (e9, bank0) register. figure 11-1. timer a control register (tacon) 8-bit timer a/b/c(0/1) s3c84bb/f84bb 11-4 block diagram notes: 1. when pwm mode, match signal cannot clear counter. 2. pending bit is located at tintpnd register. clear match tacon.7-.6 fxx/1024 fxx/256 fxx/64 tack tacon.2 pending tacon.3 overflow taovf tacap taout(tapwm) tintpnd.0 tacon.5.4 tacon.5.4 data bus 8 data bus 8 m u x m u x 8-bit up-counter (read only) 8-bit comparator timer a buffer reg timer a data register (read/write) m u x tacon.1 pending taint pg output signal tintpnd.1 figure 11-2. timer a functional block diagram s3c84bb/f84bb 8-bit timer a/b/c(0/1) 11-5 8-bit timer b overview the s3c84bb/f84bb micro-controller has an 8-bit counter called timer b. timer b, which can be used to generate the carrier frequency of a remote controller signal. pending bit of timer b is cleared automatically by hardware. timer b has two functions: ? as a normal interval timer, generating a timer b interrupt at programmed time intervals. ? to generate a programmable carrier pulse for a remote control signal at p2.4. block diagram tbcon.6-.7 fxx/1 note: in case of setting tbcon.5-.4 at '10', the value of the tbdatal register is loaded into the 8-bit counter when the operation of the timer b starts. and then if a underflow occurs in the counter, the value of the tbdatah register is loaded with the value of the 8-bit counter. however, if the next borrow occurs, the value of the tbdatal register is loaded with the value of the 8-bit counter. to output tbpwm as carrier wave, you have to set p2conh.1-.0 as "11". m u x fxx/2 fxx/4 fxx/8 tbcon.2 clk 8-bit down counter mux timer b data low byte register timer b data high byte register repeat control tbcon.0 ff tbcon.4-.5 tbcon.3 pg output signal tb underflow (tbuf) tbpwm(p2.4) irq1 (tbint) tbcon.1 data bus 8 data bus 8 figure 11-3. timer b functional block diagram 8-bit timer a/b/c(0/1) s3c84bb/f84bb 11-6 timer b control register (tbcon) timer b control register (tbcon) d0h, set 1, bank 0, r/w lsb msb.7.6.5.4.3.2.1.0 timer b mode selection bit: 0 = one-shot mode 1 = repeating mode timer b input clock selection bit: 00 = fxx/1 01 = fxx/2 10 = fxx/4 11 = fxx/8 timer b interrupt time selection bit: 00 = elapsed time for low data value 01 = elapsed time for high data value 10 = elapsed time for low and high data value 11 = invaild setting timer b start/stop bit: 0 = stop timer b 1 = start timer b timer b interrupt enable bit: 0 = disable interrupt 1 = enable interrupt timer b output flip-flop control bit: 0 = t-ff is low 1 = t-ff is high figure 11-4. timer b control register (tbcon) timer b data high-byte register (tbdatah) d1h, set 1, bank 0, r/w lsb msb.7.6.5.4.3.2.1.0 reset value: ffh timer b data low-byte register (tbdatal) d2h, set 1, bank 0, r/w lsb msb.7.6.5.4.3.2.1.0 reset value: ffh figure 11-5. timer b data registers (tbdatah, tbdatal) s3c84bb/f84bb 8-bit timer a/b/c(0/1) 11-7 timer b pulse width calculations to generate the above repeated waveform consisted of low period time, t low , and high period time, t high . when t-ff = 0, t low = (tbdatal + 1) x 1/fx, 0h < tbdatal < 100h, where fx = the selected clock. t high = (tbdatah + 1) x 1/fx, 0h < tbdatah < 100h, where fx = the selected clock. when t-ff = 1, t low = (tbdatah + 1) x 1/fx, 0h < tbdatah < 100h, where fx = the selected clock. t high = (tbdatal + 1) x 1/fx, 0h < tbdatal < 100h, where fx = the selected clock. to make t low = 24 us and t high = 15 us. f osc = 4 mhz, fx = 4 mhz/4 = 1 mhz when t-ff = 0, t low = 24 us = (tbdatal + 1) /fx = (tbdatal + 1) x 1us, tbdatal = 23. t high = 15 us = (tbdatah + 1) /fx = (tbdatah + 1) x 1us, tbdatah = 14. when t-ff = 1, t high = 15 us = (tbdatal + 1) /fx = (tbdatal + 1) x 1us, tbdatal = 14. t low = 24 us = (tbdatah + 1) /fx = (tbdatah + 1) x 1us, tbdatah = 23. 8-bit timer a/b/c(0/1) s3c84bb/f84bb 11-8 figure 11-6. timer b output flip-flop waveforms in repeat mode s3c84bb/f84bb 8-bit timer a/b/c(0/1) 11-9 programming tip ? to generate 38 khz, 1/3duty signal through p2.4 this example sets timer b to the repeat mode, sets the oscillation frequency as the timer b clock source, and tbdatah and tbdatal to make a 38 khz, 1/3 duty carrier frequency. the program parameters are: 17.59 s 37.9 khz 1/3 duty 8.795 s ? timer b is used in repeat mode ? oscillation frequency is 4 mhz (0.25 s) ? tbdatal = 8.795 s/0.25 s = 35.18, tbdatah = 17.59 s/0.25 s = 70.36 ? set p2.4 to tbpwm mode. org 0100h ; reset address start di ld tbdatah,#(70-1) ; set 17.5 s ld tbdatal,#(35-1) ; set 8.75 s ld tbcon,#00100111b ; clock source fxx ; disable timer b interrupt. ; select repeat mode for timer b. ; start timer b operation. ; set timer b output flip-flop (t-ff) high. ; ld p2conh,#03h ; set p2.4 to tbpwm mode. ; this command generates 38 khz, 1/3 duty pulse signal through p2.4. 8-bit timer a/b/c(0/1) s3c84bb/f84bb 11-10 programming tip ? to generate a one pulse signal through p2.4 this example sets timer b to the one shot mode, sets the oscillation frequency as the timer b clock source, and tbdatah and tbdatal to make a 40 s width pulse. the program parameters are: ? timer b is used in one shot mode ? oscillation frequency is 4 mhz (1 clock = 0.25 s) ? tbdatah = 40 s / 0.25 s = 160, tbdatal = 1 ? set p2.4 to tbpwm mode org 0100h ; reset address start di ld tbdatah,# (160-1) ; set 40 s ld tbdatal,# 1 ; set any value except 00h ld tbcon,#00010001b ; clock source f osc ; disable timer b interrupt. ; select one shot mode for timer b. ; stop timer b operation. ; set timer b output flip-flop (t-ff) high ld p2conh, #03h ; set p2.4 to tbpwm mode. pulse_out: ld tbcon,#00010101b ; start timer b operation ; to make the pulse at this point. ; after the instruction is executed, 0.75 s is required ; before the falling edge of the pulse starts. s3c84bb/f84bb 8-bit timer a/b/c(0/1) 11-11 8-bit timer c (0/1) overview the 8-bit timer c (0/1) is an 8-bit general-purpose timer/counter. timer c (0/1) has two operating modes, you can select one of them using the appropriate tccon0, and tccon1 setting: ? interval timer mode (toggle output at tcout0, tcout1 pin) ? pwm mode (tcout0, tcout1) timer c (0/1) has the following functional components: ? clock frequency divider with multiplexer ? 8-bit counter, 8-bit comparator, and 8-bit reference data register (tcdata0, tcdata1) ? pwm or match output (tcout0, tcout1) ? timer c (0) match/overflow interrupt (irq2, vector bch) generation ? timer c (1) match/overflow interrupt (irq2, vector beh) generation ? timer c (0) control register, tccon0 (set 1, bank1, f2h, read/write) ? timer c (1) control register, tccon1 (set 1, bank1, f3h, read/write) 8-bit timer a/b/c(0/1) s3c84bb/f84bb 11-12 timer c (0/1) control register (tccon0, tccon1) timer c control register (tccon0) f2h, set 1, bank 1, r/w, reset: 00h (tccon1) f3h, set 1, bank 1, r/w, reset: 00h lsb msb.7.6.5.4.3.2.1.0 timer c interrupt enable bit: 0 = disable interrupt 1 = enable inte rrrupt timer c 3-bits prescaler bits: 000 = non devided 001 = devided by 2 010 = devided by 3 011 = devided by 4 100 = devided by 5 101 = devided by 6 110 = devided by 7 111 = devided by 8 timer c mode selection bit: 0 = fx/1 & pwm mode 1 = fx/64 & interval mode timer c counter clear bit: 0 = no effect 1 = clear the timer a counter ( when write ) note: when the counter clear bit(.3) is set, the 8-bit counter is cleared and it also is cleared automatically. timer c pending bit: 0 = no interrupt pending 1 = interrupt pending figure 11-7. timer c (0/1) control register (tccon0, tccon1) s3c84bb/f84bb 8-bit timer a/b/c(0/1) 11-13 block diagram notes: 1. when pwm mode, match signal cannot clear counter. clear match tccon.6-.4 fxx/1 fxx/64 tccon.1 pending tccon.3 overflow tcint tcout tccon.0 data bus 8 data bus 8 3-bit pre- scaler 8-bit up-counter (read only) 8-bit comparator timer c buffer reg timer c data register (read/write) tccon.1 pending tcint tccon.0 tccon.2 m u x tccon.2 figure 11-8. timer c (0/1) functional block diagram 8-bit timer a/b/c(0/1) s3c84bb/f84bb 11-14 programming tip ? using the timer a org 0000h vector 0b8h,tamc_int vector 0bah,taov_int org 0100h initial: ld sym,#00h ; disable global/fast interrupt sym ld imr,#00000001b ; enable irq0 interrupt ld sph,#00000000b ; set stack area ld spl,#0ffh ld btcon,#10100011b ; disable watch-dog ld tadata,#80h ld tacon,#01001010b ; match interrupt enable ; 3.30 ms duration (10 mhz x?tal) ei main: ? ? main routine ? ? jr t,main tamc_int: ? ? interrupt service routine ? ? iret taov_int: ? interrupt service routine ? ? iret .end s3c84bb/f84bb 8-bit timer a/b/c(0/1) 11-15 programming tip ? using the timer b org 0000h vector 0c8h,tbun_int org 0100h initial: ld sym,#00h ; disable global/fast interrupt ld imr,#00000010b ; enable irq1 interrupt ld sph,#00000000b ; set stack area ld spl,#0ffh ld btcon,#10100011b ; disable watch-dog ld p2conh,#00000011b ; enable tbpwm output ld tbdatah,#80h ld tbdatal,#80h ld tbcon,#11101110b ; enable interrupt, repeating, fxx/8 ; duration 206 s (10 mhz x?tal) ei main: ? ? ? main routine ? ? ? jr t, main tbun_int: ? ? ? interrupt service routine ? ? ? iret .end 8-bit timer a/b/c(0/1) s3c84bb/f84bb 11-16 programming tip ? using the timer c(0) org 0000h vector 0bch, tcun_int org 0100h initial: ld sym,#00h ; disable global/fast interrupt ld imr,#00000100b ; enable irq2 interrupt ld sph,#00000000b ; set stack area ld spl,#11111111b ld btcon,#10100011b ; disable watch-dog, high speed ld p3conh,#00110000b ; enable tcout0 output ld tcdata0,#80h ld tccon0,#00001110b ; non-divide, interval, enable interrupt ; duration 0.825ms (10 mhz x?tal) ei main: ? ? ? main routine ? ? ? jr t, main tcun_int: ? ? ? interrupt service routine ? ? ? iret .end s3c84bb/f84bb 16-bit timer 1(0/1) 12-1 16-bit timer 1(0/1) overview the s3c84bb/f84bb has two 16-bit timer/counters. the 16-bit timer 1(0/1) is a 16-bit general-purpose timer/counter. timer 1(0/1) has three operating modes, one of which you select using the appropriate t1con0, t1con1 setting is: ? interval timer mode (toggle output at t1out0, t1out1 pin) ? capture input mode with a rising or falling edge trigger at the t1cap0, t1cap1 pin ? pwm mode (t1pwm0, t1pwm1); pwm output shares their output port with t1out0, t1out1 pin timer 1(0/1) has the following functional components: ? clock frequency divider (fxx divided by 1024, 256, 64, 8, or 1) with multiplexer ? external clock input pin (t1ck0, t1ck1) ? a 16-bit counter (t1cnth0/l0, t1cnth1/l1), 16-bit comparator, and two 16-bit reference data register (t1datah0/l0, t1datah1/l1) ? i/o pins for capture input (t1cap0, t1cap1), or match output (t1out0, t1out1) ? timer 1(0) overflow interrupt (irq3, vector c2h) and match/capture interrupt (irq3, vector c0h) generation ? timer 1(1) overflow interrupt (irq3, vector c6h) and match/capture interrupt (irq3, vector c4h) generation ? timer 1(0) control register, t1con0 (set 1, eah, bank 1, read/write) ? timer 1(1) control register, t1con1 (set 1, ebh, bank 1, read/write) 16-bit timer 1(0/1) s3c84bb/f84bb 12-2 function description timer 1 (0/1) interrupts (irq3, vectors c6h, c4h, c2h and c0h) the timer 1(0) module can generate two interrupts, the timer 1(0) overflow interrupt (t1ovf0), and the timer 1(0) match/capture interrupt (t1int0). t1ovf0 is interrupt level irq3, vector c2h. t1int0 also belongs to interrupt level irq3, but is assigned the separate vector address, c0h. a timer 1(0) overflow interrupt pending condition is automatically cleared by hardware when it has been serviced. a timer 1(0) match/capture interrupt, t1int0 pending condition is also cleared by hardware when it has been serviced. the timer 1(1) module can generate two interrupts, the timer 1(1) overflow interrupt (t1ovf1), and the timer 1(1) match/capture interrupt (t1int1). t1ovf1 is interrupt level irq3, vector c6h. t1int1 also belongs to interrupt level irq3, but is assigned the separate vector address, c4h. a timer 1(1) overflow interrupt pending condition is automatically cleared by hardware when it has been serviced. a timer 1(1) match/capture interrupt, t1int1 pending condition is also cleared by hardware when it has been serviced. interval mode (match) the timer 1(0) module can generate an interrupt: the timer 1(0) match interrupt (t1int0). t1int0 belongs to interrupt level irq3, and is assigned the separate vector address, c0h. in interval timer mode, a match signal is generated and t1out0 is toggled when the counter value is identical to the value written to the t1 reference data register, t1datah0/l0. the match signal generates a timer 1(0) match interrupt (t1int0, vector c0h) and clears the counter. the timer 1(1) module can generate an interrupt: the timer 1(1) match interrupt (t1int1). t1int1 belongs to interrupt level irq3, and is assigned the separate vector address, c4h. in interval timer mode, a match signal is generated and t1out1 is toggled when the counter value is identical to the value written to the t1 reference data register, t1datah1/l1. the match signal generates a timer 1(1) match interrupt (t1int1, vector c4h) and clears the counter. capture mode in capture mode for timer 1(0), a signal edge that is detected at the t1cap0 pin opens a gate and loads the current counter value into the t1 data register (t1datah0/l0 for rising edge, or falling edge). you can select rising or falling edges to trigger this operation. timer 1(0) also gives you capture input source, the signal edge at the t1cap0 pin. you select the capture input by setting the capture input selection bit in the port 3 control register, p3conl, (set 1 bank 0, f5h). both kinds of timer 1(0) interrupts (t1ovf0, t1int0) can be used in capture mode, the timer 1(0) overflow interrupt is generated whenever a counter overflow occurs, the timer 1(0) capture interrupt is generated whenever the counter value is loaded into the t1 data register (t1datah0/l0). by reading the captured data value in t1datah0/l0, and assuming a specific value for the timer 1(0) clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the t1cap0 pin. in capture mode for timer 1(1), a signal edge that is detected at the t1cap1 pin opens a gate and loads the current counter value into the t1 data register (t1datah1/l1 for rising edge, or falling edge). you can select rising or falling edges to trigger this operation. timer 1(1) also gives you capture input source, the signal edge at the t1cap1 pin. you select the capture input by setting the capture input selection bit in the port 3 control register, p3conl, (set 1 bank 0, f5h). both kinds of timer 1(1) interrupts (t1ovf1, t1int1) can be used in capture mode, the timer 1(1) overflow interrupt is generated whenever a counter overflow occurs, the timer 1(1) capture interrupt is generated whenever the counter value is loaded into the t1 data register. by reading the captured data value in t1datah1/l1, and assuming a specific value for the timer 1(1) clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the t1cap1 pin. s3c84bb/f84bb 16-bit timer 1(0/1) 12-3 pwm mode pulse width modulation (pwm) mode lets you program the width (duration) of the pulse that is output at the t1out0, t1out1 pin. as in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 1(0/1) data register. in pwm mode, however, the match signal does not clear the counter but can generate a match interrupt. the counter runs continuously, overflowing at ffffh, and then continuous increasing from 0000h. whenever an overflow is occurred, an overflow (ovf0,1) interrupt can be generated. although you can use the match or the overflow interrupt in the pwm mode, these interrupts are not typically used in pwm-type applications. instead, the pulse at the t1out0, t1out1 pin is held to low level as long as the reference data value is less than or equal to( ) the counter value and then the pulse is held to high level for as long as the data value is greater than( > ) the counter value. one pulse width is equal to t clk . timer 1(0/1) control register (t1con0, t1con1) you use the timer 1(0/1) control register, t1con0, t1con1, to ? select the timer 1(0/1) operating mode (interval timer, capture mode, or pwm mode) ? select the timer 1(0/1) input clock frequency ? clear the timer 1(0/1) counter, t1cnth0/l0, t1cnth1/l1 ? enable the timer 1(0/1) overflow interrupt ? enable the timer 1(0/1) match/capture interrupt t1con0 is located in set 1 and bank 1 at address eah, and is read/write addressable using register addressing mode. t1con1 is located in set 1 and bank 1 at address ebh, and is read/write addressable using register addressing mode. a reset clears t1con0, t1con1 to ?00h?. this sets timer 1(0/1) to normal interval timer mode, selects an input clock frequency of fxx/1024, and disables all timer 1(0/1) interrupts. to disable the counter operation, please set t1con(0/1).7-.5 to 111b. you can clear the timer 1(0/1) counter at any time during normal operation by writing a ?1? to t1con(0/1).3. to generate the exact time interval, you should write ?1? to t1con(0/1).2 and clear appropriate pending bits of the tintpnd register. to detect a match/capture or overflow interrupt pending condition when t1int0, t1int1 or t1ovf0, t1ovf1 is disabled, the application program should poll the pending bit tintpnd register, bank 0, e9h. when a ?1? is detected, a timer 1(0/1) match/capture or overflow interrupt is pending. when the sub-routine has been serviced, the pending condition must be cleared by software by writing a ?0? to the interrupt pending bit. if interrupts (match/capture or overflow) are enabled, the pending bit is cleared automatically by hardware. 16-bit timer 1(0/1) s3c84bb/f84bb 12-4 note: interrupt pending bits are located in tintpnd register. timer 1 control register (t1con0) eah, set 1, bank 1, r/w (t1con1) ebh, set 1, bank 1, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 timer 1 overflow interrupt enable bit: 0 = disable overflow interrupt 1 = enable overflow interrrupt timer 1 clock source selection bit: 000 = fxx/1024 001 = fxx 010 = fxx/256 011 = external clock(t1ck) falling edge 100 = fxx/64 101 = external clock(t1ck) rising edge 110 = fxx/8 111 = counter stop timer 1 operating mode selection bit: 00 = interval mode 01 = capture mode (capture on rising edge, ovf can occur) 10 = capture mode (capture on falling edge, ovf can occur) 11 = pwm mode (ovf and t1int can occur) timer 1 match/capture interrupt enable bit: 0 = disable interrupt 1 = enable interrrupt timer 1 counter clear bit: 0 = no effect 1 = clear counter (auto-clear bit) figure 12-1. timer 1(0/1) control register (t1con0, t1con1) s3c84bb/f84bb 16-bit timer 1(0/1) 12-5 timer a,1 pending register (tintpnd) e9h, set 1, bank 0, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 timer a overflow interrupt pending bit: not used timer a match/capture interrup t pending bit: 0 = no interrupt pending 1 = interrrupt pending timer 1(0) overflow interrupt pending bit: timer 1(0) match/capture interrupt pending bit: timer 1(1) overflow interrupt pendig bit: 0 = no interrupt pending 1 = interrupt pending timer 1(1) match/capture interrupt pending bit: 0 = no interrupt pending 1 = interrupt pending 0 = no interrupt pending 1 = interrupt pending 0 = no interrupt pending 1 = interrupt pending 0 = no interrupt pending 1 = interrupt pending figure 12-2. timer a and timer 1(0/1) pending register (tintpnd) 16-bit timer 1(0/1) s3c84bb/f84bb 12-6 block diagram fxx/1 fxx/64 fxx/8 v ss t1ck fxx/256 fxx/1024 notes: 1. when pwm mode, match signal cannot clear counter. 2. pending bit is located at tintpnd register. clear match t1con.7-.5 t1con.0 pending t1con.2 overflow t1ovf t1cap t1out t1pwm tintpnd t1con.4.3 t1con.4.3 data bus 8 data bus 8 m u x m u x 16-bit up-counter (read only) 16-bit comparator 16-bit timer buffer 16-bit timer data register (t1datah/l) m u x t1con.1 pending t1int pg output signal tintpnd figure 12-3. timer 1(0/1) functional block diagram s3c84bb/f84bb 16-bit timer 1(0/1) 12-7 programming tip ? using the timer 1(0) org 0000h vector 0e4h,t1mc_int org 0100h initial: ld sym,#00h ; disable global/fast interrupt ld imr,#00001000b ; enable irq3 interrupt ld sph,#00000000b ; set stack area ld spl,#11111111b ld btcon,#10100011b ; disable watch-dog sb1 ldw t1datah0,#0f0h ld t1con0,#01000110b ; fxx/256, interval, clear counter, enable interrupt ; duration 6.17ms (10 mhz x?tal) sb0 ei main: ? ? ? main routine ? ? ? jr t,main t1mc_int: ? ? ? interrupt service routine ? ? ? iret .end 16-bit timer 1(0/1) s3c84bb/f84bb 12-8 notes s3c84bb/f84bb serial i/o port 13-1 serial i/o port overview serial i/o module, sio can interface with various types of external devices that require serial data transfer. sio has the following functional components: ? sio data receive/transmit interrupt (irq4, vector cah) generation ? 8-bit control register, siocon (set 1, bank 1, e1h, read/write) ? clock selection logic ? 8-bit data buffer, siodata ? 8-bit prescaler (siops), (set 1, bank 1, f4h, read/write) ? 3-bit serial clock counter ? serial data i/o pins (p2.0?p2.1, so, si) ? external clock input/output pin (p2.2, sck) the sio module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control register settings. to ensure flexible data transmission rates, you can select an internal or external clock source. programming procedure to program the sio modules, follow these basic steps: 1. configure p2.1, p2.0 and p2.2 to alternative function (si, so, sck) for interfacing sio module by setting the p2conl register to appropriately value. 2. load an 8-bit value to the siocon control register to properly configure the serial i/o module. in this operation, siocon.2 must be set to "1" to enable the data shifter. 3. for interrupt generation, set the serial i/o interrupt enable bit, siocon.1 to "1". 4. to transmit data to the serial buffer, write data to siodata and set siocon.3 to 1, then the shift operation starts. 5. when the shift operation (transmit/receive) is completed, the sio pending bit (siocon.0) is set to "1" and an sio interrupt request is generated. serial i/o port s3c84bb/f84bb) 13-2 sio control register (siocon) the control register for the serial i/o interface module, siocon, is located in set 1, bank 1 at address e1h. it has the control settings for sio module. ? clock source selection (internal or external) for shift clock ? interrupt enable ? edge selection for shift operation ? clear 3-bit counter and start shift operation ? shift operation (transmit) enable ? mode selection (transmit/receive or receive-only) ? data direction selection (msb first or lsb first) a reset clears the siocon value to '00h'. this configures the corresponding module with an internal clock source, p.s clock at the sck, selects receive-only operating mode, the data shift operation and the interrupt are disabled, and the data direction is selected to msb-first. so, if you want to use sio module, you must write appropriate value to siocon. serial i/o module control registers (siocon) e1h, set 1, bank 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb sio interrupt enable bit: 0 = disable sio interrupt 1 = enable sio interrupt sio interrupt pending bit: 0 = no interrupt pending 0 = clear pending condition (when write) 1 = interrupt is pending sio shift operation enable bit: 0 = disable shifter and clock counter 1 = enable shifter and clock counter shift clock edge selection bit: 0 = t x at falling edeges, r x at rising edges 1 = t x at rising edeges, r x at falling edges data direction control bit: 0 = msb-first mode 1 = lsb-first mode sio mode selection bit: 0 = receive-only mode 1 = transmit/receive mode sio counter clear and shift start bit: 0 = no action 1 = clear 3-bit counter and start shifting sio shift clock selection bit: 0 = internal clock (p.s clock) 1 = external clock (sck) figure 13-1. sio module control register (siocon) s3c84bb/f84bb serial i/o port 13-3 sio prescaler register (siops) the control register for the serial i/o interface module, siops, is located in set 1, bank 1, at address f4h. the value stored in the sio prescaler registers, siops, lets you determine the sio clock rate (baud rate) as follows: baud rate = input clock (fxx)/[(siops value + 1) x 2] or sck input clock sio pre-scaler register (siops) f4h, set 1, bank 1, r/w .7 .6 .5 .4 .3 .2 .1 .0 msb lsb siops data value baud rate = input clock (fxx)/[(siops + 1) x 2] or sclk input cloc k figure 13-2. sio prescaler register (siops) block diagram sio int pending 3-bit counter clear siocon.0 8-bit sio shift buffer (siodata) fxx siops sck(p2.2) siocon.7 (shift clock source select) prescaled value = 1/(siops +1) clk siocon.1 (interrupt enable) clk si (p2.1) siocon.3 siocon.4 (shift clock edge select) siocon.5 (mode select) siocon.2 (shift enable) siocon.6 (lsb/msb first mode select) data bus 8 so (p2.0) m u x 1/2 8-bit p.s. irq4 figure 13-3. sio functional block diagram serial i/o port s3c84bb/f84bb) 13-4 serial i/o timing diagrams so (data output) si (data input) shift clock transmit complete irq4 set siocon.3 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 figure 13-4. sio timing in transmit/receive mode (tx at falling edge, siocon.4=0) so (data output) si (data input) shift clock transmit complete irq4 set siocon.3 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 figure 13-5. sio timing in transmit/receive mode (tx at rising edge, siocon.4=1) s3c84bb/f84bb serial i/o port 13-5 so si shift clock transmit complete irq4 set siocon.3 d7 d6 d5 d4 d3 d2 d1 d0 high impedance figure 13-6 . sio timing in receive-only mode (rising edge start) programming tip ? use internal clock to transmit and receive serial data 1. the method that uses interrupt is used. ? ? di ; disable all interrupts ld p2conl #03h ; p2.2?p2.0 are selected to alternative function for ; si, so, sck, respectively sb1 ld siodata, tdata ; load data to sio buffer ld siops, #90h ; baud rate = input clock(fxx)/[(144 + 1) x 2] ld siocon, #2eh ; internal clock, msb first, transmit/receive mode sb0 ; select tx falling edges to start shift operation ; clear 3-bit counter and start shifting ; enable shifter and clock counter ; enable sio interrupt and clear pending ei ? ? ? sioint push rp0 ; srp0 #rdata ; sb1 ld r0,siodata ; load received data to general register or siocon,#08h ; sio restart and siocon,#11111110b ; clear interrupt pending bit pop rp0 iret serial i/o port s3c84bb/f84bb) 13-6 programming tip ? use internal clock to transfer and receive serial data (continued) 2. the method that uses software pending check is used. ? ? ? di ; disable all interrupts sb1 ld siodata, tdata ; load data to sio buffer ld siops, #90h ; baud rate = input clock(fxx)/[(144 + 1) 2] ld siocon, #2ch ; internal clock, msb first, transmit/receive mode ; select falling edges to start shift operation ; clear 3-bit counter and start shifting ; disable sio interrupt and pending clear ei siotest: ld r6,siocon ; to check whether transmit and receive is finished btjrf siotest,r6.0 ; check pending bit nop and siocon,#0feh ; pending clear by software ld rdata,siodata ; load received data to rdata ? ? ? sb0 ? ? ? s3c84bb/f84bb uart(0/1) 14-1 14 uart(0/1) overview the uart block has a full-duplex serial port with programmable operating modes: there is one synchronous mode and three uart (universal asyn chronous receiver/transmitter) modes: ? serial i/o with baud rate of fxx/(16 (brdata+1)) ? 8-bit uart mode; variable baud rate ? 9-bit uart mode; fxx/16 ? 9-bit uart mode, variable baud rate uart receive and transmit buffers are both accessed via t he data register, udata0, is set 1, bank 1 at address e2h, udata1, is set 1, bank 1 at address fah. writing to the uart data register loads the transmit buffer; reading the uart data register accesses a physically separate receive buffer. when accessing a receive data buffer (shift register), rec eption of the next byte can begin before the previously received byte has been read from the receive register. howeve r, if the first byte has not been read by the time the next byte has been completely received, the first data byte will be lost. in all operating modes, transmission is started when any inst ruction (usually a write oper ation) uses the udata0, udata1 register as its destination addre ss. in mode 0, serial data recepti on starts when the receive interrupt pending bit (uartpnd.1, uartpnd.3) is "0" and the receiv e enable bit (uartcon0.4, uartcon1.4) is "1". in mode 1, 2, and 3, reception starts whenever an incomi ng start bit ("0") is received and the receive enable bit (uartcon0.4, uartcon1.4) is set to "1". programming procedure to program the uart0 modules, follow these basic steps: 1. configure p5.3 and p5.2 to alternative function rxd0, txd0 for uart0 module by setting the p5conl register to appropriatly value. 2. load an 8-bit value to the uartcon0 control regist er to properly configure the uart0 i/o module. 3. for interrupt generation, set the uart0 interrupt enable bit (uartcon0.1 or uartcon0.0) to "1". 4. when you transmit data to the uart0 buffer, wr iting data to udata0, the shift operation starts. 5. when the shift operation (transmit/receive) is comp leted, uart0 pending bit (uar tpnd.1 or uartpnd.0) is set to "1" and an uart0 interrupt request is generated. uart(0/1) s3c84bb/f84bb 14-2 uart control register (uartcon0, uartcon1) the control register for the uart is called uartcon0 in set 1, bank 1 at address e3h, uartcon1 in set 1, bank 1 at address fbh. it has the following control functions: ? operating mode and baud rate selection ? multiprocessor communication and interrupt control ? serial receive enable/disable control ? 9th data bit location for transmit and receive operations (modes 2 and 3 only) ? uart transmit and receive interrupt control a reset clears the uartcon0, uartcon1 value to "00h". so, if you want to use uart0, or uart1 module, you must write appropriate value to uartcon0, uartcon1. uart control register (uartcon0) e3h, set 1, bank 1, r/w (uartcon1) fbh, set 1, bank 1, r/w ms1 msb lsb received interrupt enable bit: 0 = disable 1 = enable transmit interrupt enable bit: 0 = disable 1 = enable location of the 9th data bit that was received in uart mode 2 or 3 ("0" or "1") serial data receive enable bit: 0 = disable 1 = enable multiprocessor communication (1) enable bit (for modes 2 and 3 only): 0 = disable 1 = enable location of the 9th data bit to be transmitted in uart mode 2 or 3 ("0" or "1") operating mode and baud rate selection bits (see table below) ms0 mce re tb8 rb8 rie tie ms1 ms0 0 0 1 1 0 1 0 1 mode description (2) baud rate 0 1 2 3 shift register 8-bit uart 9-bit uart 9-bit uart fxx/(16 x (brdata + 1)) fxx/(16 x (brdata + 1)) fxx/16 fxx/(16 x (brdata + 1)) notes: 1. in mode 2 or 3, if the uartcon.5 bit is set to "1" then the receive interrupt will not be activated if the received 9th data bit is "0". in mode 1, if uartcon.5 = "1" then the receive interrut will not be activated if a valid stop bit was not received. in mode 0, the uartcon.5 bit should be "0" 2. the descriptions for 8-bit and 9-bit uart mode do not include start and stop bits for serial data receive and transmit. figure 14-1. uart control register (uartcon0, uartcon1) s3c84bb/f84bb uart(0/1) 14-3 uart interrupt pending register (uartpnd) the uart interrupt pending register, uartpnd is located in set 1, bank 1 at address e5h, it contains the uart0 data transmit interrupt pending bit (uartpnd.0), the receive interrupt pending bit (uartpnd.1), the uart1 data transmit interrupt pending bit (uartpnd.2) , and the receive interrupt pending bit (uartpnd.3). in mode 0, the receive interrupt pendi ng flag uartpnd.1, uartpnd.3 is set to "1" when the 8th receive data bit has been shifted. in mode 1, 2, and 3, the uartpnd.1, uartpnd.3 bit is set to "1" at the halfway point of the stop bit's shift time. when the cpu has acknowledged t he receive interrupt pending c ondition, the uartpnd.1, uartpnd.3 flag must then be cleared by softw are in the interrupt service routine. in mode 0, the transmit interrupt pending flag uartpnd.0, uartpnd.2 is set to "1" when the 8th transmit data bit has been shifted. in mode 1, 2, or 3, the uartpnd.0, uartpnd.2 bit is set at t he start of the stop bit. when the cpu has acknowledged the transmit interrupt pending condition, the uartpnd.0, uartpnd.2 flag must then be cleared by software in t he interrupt service routine. uart pending register (uartpnd) e5h, set 1, bank 1, r/w - msb lsb uart0 receive interrupt pending flag: 0 = not pending 0 = clear pending bit (when write) 1 = interrupt pending uart0 transmit interrupt pending flag: 0 = not pending 0 = clear pending bit (when write) 1 = interrupt pending not used --- rip1 tip1 rip0 tip0 notes: 1. in order to clear a data transmit or receive interrupt pending flag, you must write a "0" to the appropriate pending bit. 2. to avoid errors, we recommend using load instruction (except for ldb), when manipulating uartpnd values. uart1 transmit interrupt pending flag: 0 = not pending 0 = clear pending bit (when write) 1 = interrupt pending uart1 receive interrupt pending flag: 0 = not pending 0 = clear pending bit (when write) 1 = interrupt pending figure 14-2. uart interrupt pending register (uartpnd) uart(0/1) s3c84bb/f84bb 14-4 uart data register (udata0, udata1) uart data register (udata0) e2h, set 1, bank 1, r/w (udata1) fah, set 1, bank 1, r/w .7 msb lsb transmit or receive data .6 .5 .4 .3 .2 .1 .0 figure 14-3. uart data register (udata0, udata1) uart baud rate data register (brdata0, brdata1) the value stored in the uart0 baud rate register, brda ta0, lets you determine the uart0 clock rate (baud rate). the value stored in the uart1 baud rate register , brdata1, lets you deter mine the uart1 clock rate (baud rate). uart baud rate data register (brdata0) e4h, set 1, bank 1, r/w (brdata1) fch, set 1, bank 1, r/w .7 msb lsb baud rate data .6 .5 .4 .3 .2 .1 .0 figure 14-4. uart baud rate data register (brdata0, brdata1) baud rate calculations (uart0) mode 0 baud rate calculation in mode 0, the baud rate is determined by the uart0 baud rate data register, brdata0 in set1, bank 1 at address e4h. mode 0 baud rate = fxx/(16 (brdata0 + 1)) mode 2 baud rate calculation the baud rate in mode 2 is fixed at the f osc clock frequency divided by 16: mode 2 baud rate = fxx/16 modes 1 and 3 baud rate calculation in modes 1 and 3, the baud rate is determined by the ua rt0 baud rate data register, brdata0 in set 1, bank 1 at address e4h. mode 1 and 3 baud rate = fxx/(16 (brdata0 + 1)) s3c84bb/f84bb uart(0/1) 14-5 table 14-1. commonly used baud rates generated by brdata0, brdata1 mode baud rate oscillation clock brdata0, brdata1 decimal hexdecimal mode 2 0.5 mhz 8 mhz x x mode 0 230,400 hz 11.0592 mhz 02 02h mode 1 115,200 hz 11.0592 mhz 05 05h mode 3 57,600 hz 11.0592 mhz 11 0bh 38,400 hz 11.0592 mhz 17 11h 19,200 hz 11.0592 mhz 35 23h 9,600 hz 11.0592 mhz 71 47h 4,800 hz 11.0592 mhz 143 8fh 62,500 hz 10 mhz 09 09h 9,615 hz 10 mhz 64 40h 38,461 hz 8 mhz 12 0ch 12,500 hz 8 mhz 39 27h 19,230 hz 4 mhz 12 0ch 9,615 hz 4 mhz 25 19h uart(0/1) s3c84bb/f84bb 14-6 block diagram zero detector uartdata rxd0 (p5.3 ) rxd1 (p5.1 ) tie rie irq7 interrupt 1-to-0 transition detector re rie bit detector shift value ms0 ms1 ms0 ms1 rxd0 (p5.3) rxd1 (p5.1) sam8 internal data bus write to uartdata baud rate generator s dq clk tb8 clk tx control start tx clock tip shift en send rx control rx clock start rip receive shift shift clock ms0 ms1 fxx sam8 internal data bus shift register uartdata brdata txd0 (p5.2) txd1 (p5.0) txd0 (p5.2) txd1 (p5.0) figure 14-5. uart functional block diagram s3c84bb/f84bb uart(0/1) 14-7 uart0 mode 0 function description in mode 0, uart0 is input and output through the rxd0 (p 5.3) pin and txd0 (p5.2) pi n outputs the shift clock. data is transmitted or received in 8-bi t units only. the lsb of the 8-bit va lue is transmitted (or received) first. mode 0 transmit procedure 1. select mode 0 by setting uartcon0.6 and .7 to "00b". 2. write transmission data to the shift register udata0 (e 2h, set 1, bank 1) to start the transmission operation. mode 0 receive procedure 1. select mode 0 by setting uatcon0.6 and .7 to "00b". 2. clear the receive interrupt pending bit (uar tpnd.1) by writing a "0" to uartpnd.1. 3. set the uart0 receive enable bit (uartcon0.4) to "1". 4. the shift clock will now be output to the txd0 (p5. 2) pin and will read the data at the rxd0 (p5.3) pin. a uart0 receive interrupt (irq7, vector f0h) occurs when uartcon0.1 is set to "1". transmit d0 d1 d2 d3 d4 d5 d6 d7 write to shift register (udata) rxd (data out) txd (shift clock) tip shift receive write to uartpnd (clear rip and set re) shift d0 d1 d2 d3 d4 d5 d6 d7 txd (shift clock) rxd (data in) re rip 12345678 figure 14-6. timing diagram for uart mode 0 operation uart(0/1) s3c84bb/f84bb 14-8 uart0 mode 1 function description in mode 1, 10-bits are transmitted through the txd0 pin or received through the rxd0 pin. each data frame has three components: ? start bit ("0") ? 8 data bits (lsb first) ? stop bit ("1") when receiving, the stop bit is written to the rb8 bit in the uartcon0 register. the baud rate for mode 1 is variable. mode 1 transmit procedure 1. select the baud rate gener ated by setting brdata0. 2. select mode 1 (8-bit uart0) by se tting uartcon0 bits 7 and 6 to '01b'. 3. write transmission data to the shift register udata 0 (e2h, set 1, bank 1). the start and stop bits are generated automatically by hardware. mode 1 receive procedure 1. select the baud rate to be generated by setting brdata0. 2. select mode 1 and set the re (receive enabl e) bit in the uartcon0 register to "1". 3. the start bit low ("0") condition at the rxd0 (p5.3) pin will cause the uart0 module to start the serial data receive operation. transmit tip write to shift register (udata) start bit txd stop bit d0 d1 d2 d3 d4 d5 d6 d7 shift tx clock receive rip start bit rx clock stop bit rxd d0 d1 d2 d3 d4 d5 d6 d7 bit detect sample time shift figure 14-7. timing diagram for uart mode 1 operation s3c84bb/f84bb uart(0/1) 14-9 uart0 mode 2 function description in mode 2, 11-bits are transmitted (through the txd0 pin) or received (through the rxd0 pin). each data frame has four components: ? start bit ("0") ? 8 data bits (lsb first) ? programmable 9th data bit ? stop bit ("1") the 9th data bit to be transmitted can be assigned a value of "0" or "1" by writing the tb8 bit (uartcon0.3). when receiving, the 9th data bit that is received is written to the rb8 bi t (uartcon0.2), while the stop bit is ignored. the baud rate for mode 2 is fosc/16 clock frequency. mode 2 transmit procedure 1. select mode 2 (9-bit uart0) by setting uartcon0 bi ts 6 and 7 to '10b'. also, select the 9th data bit to be transmitted by writing tb8 to "0" or "1". 2. write transmission data to the shift register, udata0 (e2h, set 1, bank 1), to st art the transmit operation. mode 2 receive procedure 1. select mode 2 and set the receive enable bit (re) in the uartcon0 register to "1". 2. the receive operation starts when the si gnal at the rxd pin goes to low level. transmit tip write to shift register (uartdata) start bit txd stop bit d0 d1 d2 d3 d4 d5 d6 d7 shift tx clock receive rip start bit rx clock stop bit rxd d0 d1 d2 d3 d4 d5 d6 d7 bit detect sample time shift tb8 rb8 figure 14-8. timing diagram for uart mode 2 operation uart(0/1) s3c84bb/f84bb 14-10 uart0 mode 3 function description in mode 3, 11-bits are transmitted (through the txd0) or received (through the rxd0). mode 3 is identical to mode 2 except for baud rate, which is variabl e. each data frame has four components: ? start bit ("0") ? 8 data bits (lsb first) ? programmable 9th data bit ? stop bit ("1") mode 3 transmit procedure 1. select the baud rate gener ated by setting brdata0. 2. select mode 3 operation (9-bit uart 0) by setting uartcon0 bits 6 and 7 to '11b'. also, select the 9th data bit to be transmitted by writing uartcon0.3 (tb8) to "0" or "1". 3. write transmission data to the shift register, udata0 (e2h, set 1, bank 1), to st art the transmit operation. mode 3 receive procedure 1. select the baud rate to be generated by setting brdata0. 2. select mode 3 and set the re (receive enabl e) bit in the uartcon0 register to "1". 3. the receive operation will be started when the signal at the rxd0 pin goes to low level. transmit tip write to shift register (uartdata) start bit txd stop bit d0 d1 d2 d3 d4 d5 d6 d7 shift tx clock receive rip start bit rx clock stop bit rxd d0 d1 d2 d3 d4 d5 d6 d7 bit detect sample time shift tb8 rb8 figure 14-9. timing diagram for uart mode 3 operation s3c84bb/f84bb uart(0/1) 14-11 serial communication for multiprocessor configurations the s3c8-series multiprocessor communication feature lets a "master" s3c84bb/ s3f84bb send a multiple- frame serial message to a "slave" device in a multi- s3c84bb/f84bb configurati on. it does this without interrupting other slave devices that may be on the same serial line. this feature can be used only in uart modes 2 or 3. in these modes 2 and 3, 9 data bits are received. the 9th bit value is written to rb8 (uartcon0.2, or uartcon1 .2). the data receive operation is concluded with a stop bit. you can program this function so that when the stop bit is received, the serial interrupt will be generated only if rb8 = "1". to enable this feature, you set the mce bit in the uart con0/1 register. when the mce bit is "1", serial data frames that are received with the 9th bit = "0" do not generate an interrupt. in this case, the 9th bit simply separates the address from the serial data. sample protocol for master/slave interaction when the master device wants to transmit a block of data to one of several slaves on a serial line, it first sends out an address byte to identify the target slave. note that in this case, an addr ess byte differs from a data byte: in an address byte, the 9th bit is "1" and in a data byte, it is "0". the address byte interrupts all slaves so that each slav e can examine the received byte and see if it is being addressed. the addressed slave then clears its mce bi t and prepares to receive incoming data bytes. the mce bits of slaves that were not addressed rema in set, and they continue operating normally while ignoring the incoming data bytes. while the mce bit setting has no effect in mode 0, it c an be used in mode 1 to check the validity of the stop bit. for mode 1 reception, if mce is "1", the receive inte rrupt will be issue unless a valid stop bit is received. uart(0/1) s3c84bb/f84bb 14-12 setup procedure for multiprocessor communications follow these steps to configure multiprocessor communications: 1. set all s3c84bb/f84bb devices (maste rs and slaves) to uart mode 2 or 3. 2. write the mce bit of all the slave devices to "1". 3. the master device's transmission protocol is: ? first byte: the address identifying the target slave device (9th bit = "1") ? next bytes: data (9th bit = "0") 4. when the target slave receives the first byte, all of the slaves are inte rrupted because the 9th data bit is "1". the targeted slave compares the address byte to it s own address and then clears its mce bit in order to receive incoming data. the other slaves continue operating normally. full-duplex multi-s3c84bb/f84bb interconnect . . . txd rxd master s3c84bb/f84bb txd rxd slave 1 s3c84bb/f84bb txd rxd slave 2 s3c84bb/f84bb txd rxd slave n s3c84bb/f84bb figure 14-10. connection example for mult iprocessor serial data communications s3c84bb/f84bb 10-bit a/d converter 15-1 10-bit a/d converter overview the 10-bit a/d converter (adc) module uses successive approximation logic to convert analog levels entering at one of the eight input channels to equivalent 10-bit digital values. the analog input level must lie between the av ref and av ss values. the a/d converter has the following components: ? analog comparator with successive approximation logic ? d/a converter logic (resistor string type) ? adc control register, adacon (set 1, bank 1, f7h, read/write, but adcon.3 is read only) ? eight multiplexed analog data input pins (adc0?adc7) ? 10-bit a/d conversion data output register (addatah, addatal) ? internal av ref and av ss function description to initiate an analog-to-digital conversion procedure, at first, you must configure p7.0?p7.7 to analog input before a/d conversions because the p7.0 ? p7.7 pins can be used alternatively as normal data input or analog input pins. to do this, you load the appropriate value to the p7con.0 ? p7con.7 (for adc0 ? adc7) register. and you write the channel selection data in the a/d converter control register adacon to select one of the eight analog input pins (adcn, n = 0?7) and set the conversion start or enable bit, adacon.0. an 10-bit conversion operation can be performed for only one analog input channel at a time. the read-write adacon register is located in set 1, bank 1 at address f7h. during a normal conversion, adc logic initially sets the successive approximation register to 200h (the approximate half-way point of an 10-bit register). this register is then updated automatically during each conversion step. the successive approximation block performs 10-bit conversions for one input channel at a time. you can dynamically select different channels by manipulating the channel selection bit value (adacon.6?4) in the adacon register. to start the a/d conversion, you should set the enable bit, adacon.0. when a conversion is completed, adacon.3, the end-of-conversion (eoc) bit is automatically set to 1 and the result is dumped into the addatah, addatal registers where it can be read. the adc module enters an idle state. remember to read the contents of addatah and addatal before another conversion starts. otherwise, the previous result will be overwritten by the next conversion result. note because the adc does not use sample-and-hold circuitry, it is important that any fluctuations in the analog level at the adc0?adc7 input pins during a conversion procedure be kept to an absolute minimum. any change in the input level, perhaps due to circuit noise, will invalidate the result. 10-bit a/d converter s3c84bb/f84bb 15-2 a/d converter control register (adacon) the a/d converter control register, adacon, is located in set1, bank 1 at address f7h. adacon is read-write addressable using 8-bit instructions only. but eoc bit, adacon.3 is read only. adacon has four functions: ? bits 6?4 select an analog input pin (adc0?adc7). ? bit 3 indicates the end of conversion status of the a/d conversion. ? bits 2?1 select a conversion speed. ? bit 0 starts the a/d conversion. only one analog input channel can be selected at a time. you can dynamically select any one of the eight analog input pins, adc0?adc7 by manipulating the 3-bit value for adacon.6?adacon.4 a/d start or enable bit 0 = disable operation 1 = start operation a/d, d/a converter control register (adacon) f7h, set 1, bank 1, r/w (adcon.3 bit is read-only) .7 .6 .5 .4 .3 .2 .1 .0 msb lsb end-of-conversion bit (read only): 0 = conversion not complete 1 = conversion complete a/d input pin selection bits: a/d input pin clock selection bit: .4 .5 000 001 010 011 100 101 110 111 adc0 adc1 adc2 adc3 adc4 adc5 adc6 adc7 conversion clock .1 .2 0 1 0 1 0 0 1 1 fxx/16 fxx/8 fxx/4 fxx .6 d/a start or enable bit 0 = disable operation 1 = start operation figure 15-1. a/d converter control register (adacon) s3c84bb/f84bb 10-bit a/d converter 15-3 conversion data register high byte (addatah) f8h, set 1, bank 1, read only lsb msb.7.6.5.4.3.2.1.0 conversion data register low byte (addatal) f9h, set 1, bank 1, read only lsb msbxxxxxx.1.0 figure 15-2. a/d converter data register (addatah, addatal) input pins adc0-adc7 (p7.0-p7.7) 10-bit result is loaded into a/d conversion data register to adacon.3 (eoc flag) av ref av ss analog comparator adacon.4-.6 (select one input pin of the assigned) adacon.0 (ad/c enable) adacon.0 (a/d conversion enable) adacon.2-.1 m u l t i p l e x e r + - clock selector successive approximation logic 10-bit d/a converter conversion result (addatah,addatal) to data figure 15-3. a/d converter circuit diagram 10-bit a/d converter s3c84bb/f84bb 15-4 internal reference voltage levels in the adc function block, the analog input voltage level is compared to the reference voltage. the analog input level must remain within the range av ss to av ref (usually av ref = v dd ). different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. the reference voltage level for the first bit conversion is always 1/2 av ref . conversion timing the a/d conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to step-up a/d conversion. therefore, total of 50 clocks is required to complete a 10-bit conversion. with a 10 mhz cpu clock frequency, one clock cycle is 400 ns (4/fxx). if each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit x 10-bits + step-up time (10 clock) = 50 clocks 50 clock x 400 ns = 20 s at 10 mhz, 1 clock time = 4/fxx 50 adc clock 40 clock addatah (8-bit) + addatal (2-bit) ! " # $ $ % & figure 15-4. a/d converter timing diagram s3c84bb/f84bb 10-bit a/d converter 15-5 internal a/d conversion procedure 1. analog input must remain between the voltage range of av ss and av ref . 2. configure p7.0?p7.7 for analog input before a/d conversions. to do this, you load the appropriate value to the p7con (for adc0?adc7) register. 3. before the conversion operation starts, you must first select one of the eight input pins (adc0?adc7) by writing the appropriate value to the adacon register. 4. when conversion has been completed, (50 clocks have elapsed), the eoc, adacon.3 flag is set to "1", so that a check can be made to verify that the conversion was successful. 5. the converted digital value is loaded to the output register, addatah (8-bit) and addatal (2-bit), then the adc module enters an idle state. 6. the digital conversion result can now be read from the addatah and addatal register. reference voltage input analog input note: the symbol "r1" signifies an offset resistor with a value of from 50 to 100 ? . if this resistor is omitted, the absolute accuracy will be maximum of 3lsbs. c1=10 f, c2=100 to 1000pf, c3=100 to 1000pf, r1=50 to 100 ? , r2=10 to 1k ? . s3c84bb/ f84bb adc0-adc7 av ref r1 v dd av ss c2 c1 r2 c3 v ss figure 15-5. recommended a/d converter circuit for highest absolute accuracy 10-bit a/d converter s3c84bb/f84bb 15-6 programming tip ? configuring a/d converter sb0 ld p7con,#11111111b ; p7.7?p7.0 a/d input mode sb1 ld adacon,#00000001b ; channel adc0, conversion start ad0_chk: tm adacon,#00001000b ; a/d conversion end ? eoc check jr z, ad0_chk ; no ld ad0bufh,addatah ; 8-bit conversion data ld ad0bufl,addatal ; 2-bit conversion data sb0 sb1 ld adacon,#00110001b ; channel ad3, fxx/16, conversion start ad3_chk: tm adacon,#00001000b ; a/d conversion end ? eoc check jr z,ad3_chk ; no ld ad3bufh,addatah ; 8-bit conversion data ld ad3bufl,addatal ; 2-bit conversion data sb0 s3c84bb/f84bb 8-bit d/a converter 16-1 8-bit d/a converter overview the s3c84bb/f84bb has 8-bit digital-to-analog converter with r-2r structure. this dac(digital-to-analog) is used to generate analog voltage, v da , with 256 steps(2 8 ) the function is controlled by adacon. to enable the converter, the adacon.7 must be set to?1?. to generate analog voltage(v da ), load the appropriate value to dadata. the level of analog voltage is determined by dadata. ? d/a converter logic (resistor string type) ? 8-bit d/a conversion data register, dadata (set 1, bank1, f6h, read/write) 8-bit d/a converter s3c84bb/f84bb 16-2 d/a converter control register (adacon) the digital-to-analog converter (dac) control register, adacon, is a 8-bit register located at f7h (set1, bank1). adacon register controls to enable or disable the digital-to-analog converter (dac). a/d start or enable bit 0 = disable operation 1 = start operation a/d, d/a converter control register (adacon) f7h, set 1, bank 1, r/w (adcon.3 bit is read-only) .7 .6 .5 .4 .3 .2 .1 .0 msb lsb end-of-conversion bit (read only): 0 = conversion not complete 1 = conversion complete a/d input pin selection bits: a/d input pin clock selection bit: .4 .5 000 001 010 011 100 101 110 111 adc0 adc1 adc2 adc3 adc4 adc5 adc6 adc7 conversion clock .1 .2 0 1 0 1 0 0 1 1 fxx/16 fxx/8 fxx/4 fxx .6 d/a start or enable bit 0 = disable operation 1 = start operation figure 16-1. d/a converter control register (adacon) d/a converter data register (dadata) dadata, is a 8-bit read and write register located at f6h (set1, bank1). the dadata specifies the digital data to generate analog voltage. adacon values are set to logic ?0? following reset and the value disable dac. conversion data register byte (dadata) f6h, set 1, bank 1, r/w lsb msb.7.6.5.4.3.2.1.0 figure 16-2. d/a converter data register (dadata) these are the values be determined by setting just one-bit of dadata.0-dadata.7. the other values of daout can be obtained with superimposition. s3c84bb/f84bb 8-bit d/a converter 16-3 block diagram dadata .0 .1 .2 .3 .4 .5 .6 .7 2r 2r 2r 2r 2r 2r 2r 2r 2r daout r rrrr rr adacon.7 figure 16-3. d/a converter circuit diagram table 16-1. dadata setting to generate analog voltage dadata7 dadata6 dadata5 dadata4 dadata3 dadata2 dadata1 dadata0 v daout 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 vdd/2 1 0 1 0 0 0 0 0 0 vdd/2 2 0 0 1 0 0 0 0 0 vdd/2 3 0 0 0 1 0 0 0 0 vdd/2 4 0 0 0 0 1 0 0 0 vdd/2 5 0 0 0 0 0 1 0 0 vdd/2 6 0 0 0 0 0 0 1 0 vdd/2 7 0 0 0 0 0 0 0 1 vdd/2 8 8-bit d/a converter s3c84bb/f84bb 16-4 notes s3c84bb/f84bb pattern generation module 17-1 pattern generation module overview pattern generation flow you can output up to 8-bit through p0.0-p0.7 by tracing the following sequence. first of all, you have to change the pgdata into what you want to output. and then you have to set the pgcon to enable the pattern generation module and select the triggering signal. from now, bits of pgdata are on the p0.0-p0.7 whenever the selected triggering signal occurs. write pattern data to pgdata triggering signal selection: pgcon.3-.0 triggering signal generation data output through p0.0-p0.7 figure 17-1. pattern generation flow pattern generation module s3c84bb/f84bb 17-2 bit3: 0 = no effect 1 = s/w trigger start (auto clear) pattern generation module control register (pgcon) feh, set 1, bank 1, r/w msb.7.6.5.4.3.2.1.0 not used bit2: 0 = pg operation disable 1 = pg operation enable pg operation mode selection bit 00 01 10 11 timer a match signal triggering timer b underflow signal triggering timer 1(0) match signal triggering s/w triggering mode figure 17-2. pg control register (pgcon) .7 .6 .5 .4 .3 .2 .1 .0 pg buffer pgdata (set 1, bank 1, ffh) s/w timer a match signal timer b underflow signal timer 1(0) match signal p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 .7 .6 .5 .4 .3 .2 .1 .0 figure 17-3. pattern generation circuit diagram s3c84bb/f84bb pattern generation module 17-3 programming tip ? using the pattern generation org 0000h org 0100h initial: sb0 ld sym,#00h ; disable global interrupt sym ld imr,#01h ; enable irq0 interrupt ld sph,#0h ; high byte of stack pointer sph ld spl,#0ffh ; low byte of stack pointer spl ld btcon,#10100011b ; disable watch-dog ld clkcon,#00011000b ; non-divided ld p0con,#11111111b ; enable pg output ei main: nop nop sb1 ld pgdata,#10101010b ; setting pattern data or pgcon,#00001111b ; triggering then pattern data are output sb0 nop nop jr t,main .end pattern generation module s3c84bb/f84bb 17-4 notes s3c84bb/f84bb embedded flash memory interface 18-1 18 embedded flash memeory interface overview the s3f84bb has an on-chip flash eeprom instead of ma sked rom. the flash eeprom is accessed by serial data format and the type of a full flash, that is, a user can program the data in a flash memory area any time you wants. the flash eeprom endurance is 100 cycles for erase/program operation. the s3f84bb?s embedded 64k-byte memory has several operating features below: the s3f84bb has 6 pins used to read/write the flas h memory, vdd/vss, reset, test, sdat and sclk. the flash memory control block suppor ts two kinds of program mode: ? tool program mode ? user program mode tool program mode the 6 pins are connected to a programming tool and pr ogrammed by serial otp/mtp tools (spw2plus single programmer, or gw-pro2 gang programmer). the 12.5v progr amming power is supplied into the vpp (test) pin. the other modules except flash eepr om module are at a reset state. this mode doesn?t support sector erase but chips eras e and two protection modes (hard lock protection/ read protection). user program mode this mode supports sector er ase and two protection modes. the s3f84bb has the pumping circuit internally, therefore, 12.5v into vpp (test) pin is not needed. to program a flash memory in this mode several control registers will be used, refer to page 18-2. during programming/erasing flash memory, cpu will be held (30us) automatically. two signals, sclk, sdat should be made in user pr ogram mode by using fsclk and fsdat bit in fmcon register (address fdh in set1, bank1) in order to program a flash memory. there are three kind functions ? sector erase, progra mming, option sector programming in user program mode. serial interface protocol format serial interface protocol format consist of 3-byte address field and two and more byte data field. in the 1st byte of address field, 4-bits are assigned for serial interface mode, the other 4-bits are assigned for address extension. (see figure 18-4, and 18-5) data valid status of sclk: high data invalid status of sclk: low start condition : sclk = high, and sdat = positive edge stop condition : sclk = high, and sdat = negative edge embedded flash memory interface s3c84bb/f84bb 18-2 table 18-1. command in user program mode ? 1st byte 2nd byte 3rd byte ? mode reg/ memb mode (m1-m0) address (a19-a16) r/wb address (a15-a8) address (a7-a0) data (d7-d0) bit n b23 b22-b21 b20-b17 b16 b15-b8 b7-b0 available program mode program 0 11b xxxxb 0 xxh xxh xxh tool,user program mode hard lock protection 1 11b 0000b 0/1 ---0, 1110b --11, 1110b ----, --0-b tool,user program mode read protection 1 11b 0000b 0/1 ---0, 1110b --11, 1111b ----, 0---b tool,user program mode sector erase 0 10b xxxxb 0 xxh xxh ----, ----b user program mode only s3c84bb/f84bb embedded flash memory interface 18-3 flash memory control registers flash memory control register fmcon register is available only in user program mode to program some data to the flash memory. flash memory control register (fmcon) fdh, set 1, bank 1, r/w lsb msb.7.6.5.4.3.2.1.0 user programming serial clock bit: 0 = fsclk is low 1 = fsclk is high user programming serial data bit: 0 = fsdat is low 1 = fsdat is high user programming mode status bit: 0 = not-user programming mode 1 = user programming mode figure 18-1. flash memory control register (fmcon) flash memory user programming enable register ram address (00h) of page 8 is used as flash memory e nable register. this location can be addressed by 1-bit or 8-bit instructions. after reset, the user-programming mode is dis abled, because the value of fmusr is ?00000000b?. if necessary, you can use the user programming mode by setting the value of fmusr is ?10100101?. flash memory user programming enable register (fmusr) 00h, page 8, r/w lsb msb .7 .6 .5 .4 .3 .2 .1 .0 flash memory user programming enable bits: 00000000 : disable user programming mode 10100101 : enable user programming mode figure 18-2. flash memory user programming enable register (fmusr) embedded flash memory interface s3c84bb/f84bb 18-4 the program procedure in user program mode 1. set flash memory control register (fmcon.1) properly to access flash memory 2. clear fsclk (fmcon.0) bit, fsdat (fmcon.7) bi t for the initialization of sclk and sdat signals 3. enter into sector program mode with instruct ions of ?ld pp, #88h?,?ld 00h,#0a5h? orderly. 4. make sclk, sdat signals for start condition with controlling fsclk, fsdat bits in fmcon register. 5. make sclk, sdat signals for 3-byte address fiel d with controlling fsclk, and fsdat bits in fmcon register. 6. make sclk, sdat signals for data field with c ontrolling fsclk, and fsdat bits in fmcon register. 7. make sclk, sdat signals for 1-byte dummy data with controlling fsclk, and fsdat bits in fmcon register. 8. make sclk, sdat signals for stop condition by c ontrolling fsclk, and fsdat bits in fmcon register. 9. release user program mode with instruction of ?ld pp, #88h?, and ?ld 00h, #00h? orderly. s3c84bb/f84bb embedded flash memory interface 18-5 sector erase user can erase a flash memory par tially by using sector erase f unction only in user program mode. the only unit of flash memory to be erased and wr itten in user program mode is called sector. s3f84bb has 120 sectors to be erased written in flash memory. sectors have all 512-byte sizes as program memory areas. sector erase is not supported in tool program modes (mds mode). minimum 2ms to maximum 100ms delay time for erase is required after setting sector address. (hex) ffffh 1000h sector 0 (512 byte) 4-kbyte 0000h 11ffh 0fffh not-writible in user program mode (flash program memory) writible in user program mode (flash program memory) 13ffh sector 1 (512 byte) sector 119 (512 byte) fdffh figure 18-3. sectors in user program mode embedded flash memory interface s3c84bb/f84bb 18-6 s dummy clk 12-789 12-789 12-789 a23 a22-a17a16 dummy clk a15-a8 dummy clk a7-a0 12-789 d7-d0 sdat sclk 1'st byte 2'nd byte 3'rd byte data = ffh dummy clk 12-789 d7-d0 sdat sclk data = ffh dummy clk sector erase delay = typ. 3ms p (dummy data for the time to write last data) lasr data = always "ff" 1st-3rd byte (address field) -010x xxx0b, yyh, zzh the yy, zzh is a sector address figure 18-4. sectors erase wave form s3c84bb/f84bb embedded flash memory interface 18-7 programming tip ? sector erase sb1 clr fmcon ; clear register sb0 ld clkcon, #00h ; cpu clock is 16-divide loope: nop ld pp, #88h ; ld 00h,#0a5h ; user program mode enable ld pp,#00h ; sb1 ent: or fmcon,#00000010b ; flag enable tm fmcon,#00000010b ; flag check jr z, ent sb0 spgm: sb1 ; start or fmcon,#00000001b ; sclk=1 or fmcon,#10000000b ; sdat=1 sb0 ld r8,#01000000b ; 1?st byte (sector erase mode) call pgm ld r8,#00010000b ; 2nd byte, address=1000h (sector 0) call pgm ld r8,#00000000b ; 3rd byte call pgm ld r15,#0ebh ; delay for typical 3ms when 10mhz oscillator used delay: djnz r15,delay ; ((1/(10mhz/16))x8cycle) x 235 = 3.008 [ms] ld r8,#0ffh ; dummy data call pgm sb1 and fmcon,#01111111b ; sdat=0 and fmcon,#11111110b ; sclk=0, stop sb0 ld pp,#88h ld 00h,#00h ; user program mode disable ld pp,#00h embedded flash memory interface s3c84bb/f84bb 18-8 programming tip ? sector erase (continued) sb1 rel: and fmcon,#11111101b ; flag disable tm fmcon,#00000010b ; flag check jr nz, rel sb0 jp end_sym ; end pgm: sb1 and fmcon,#11111110b ; sclk=0 call wait ld r9, #08h ; rotate time pgmb: rl r8 ; msb -> lsb ldb fmcon.7,r8 ; fmcon.7 ? r8.0 or fmcon,#00000001b ; sclk=1 and fmcon,#11111110b ; sclk=0 djnz r9, pgmb or fmcon,#10000000b ; sdat=1 or fmcon,#00000001b ; sclk=1 sb0 ret wait: nop nop ld r15, #0ffh ; 00h <- ffh loop0: djnz r15, loop0 ret end_sym: nop .end s3c84bb/f84bb embedded flash memory interface 18-9 programming a flash memory is programmed in one byte unit after sector erase. the write operation of programming starts at a falli ng edge of dummy clock when a start address and data have been transmitted, and finishes at a falling edge of last sclk for next data transmission. the next data to write is transmitted during the previous dat a is writing. so, s3f84bb has 8-bit buffer register to write data to flash cell and shift register to receive the next data to be written. the address of next data increments aut omatically at a dummy clock afte r previous data has been transmitted. dummy data (ffh) is required after transmission of the last data because the time to write the last data to flash cell is needed. programming finished when stop condition occurs after the dummy clock has been transmitted. s dummy clk 12-789 12-789 12-789 a23 a22-a17a16 dummy clk a15-a8 dummy clk a7-a0 12-789 d7-d0 sdat sclk 1'st byte 2'nd byte 3'rd byte data dummy clk 12-789 d7-d0 sdat sclk data = ffh dummy clk p (dummy data for the time to write last data) lasr data = always "ff" 12-789 12-789 dummy clk d7-d0 d7-d0 data + n data + n +1 figure 18-5. program wave form embedded flash memory interface s3c84bb/f84bb 18-10 programming tip ? programming sb1 clr fmcon ; clear register sb0 ld clkcon, #00h ; cpu clock is 16-divide loope: nop ld pp, #88h ; ld 00h,#0a5h ; user program mode enable ld pp,#00h ; sb1 ent: or fmcon,#00000010b ; flag enable tm fmcon,#00000010b ; flag check jr z, ent sb0 spgm: sb1 ; start or fmcon,#00000001b ; sclk=1 or fmcon,#10000000b ; sdat=1 sb0 ld r8,#01100010b ; 1?st byte (programming mode) call pgm ld r8,#00010000b ; 2nd byte, address=1000h (sector 0) call pgm ld r8,#00000000b ; 3rd byte call pgm ld r3, #00h ; write address = 1000h ~ 10ffh adr: ld r8, #66h ; write data = 66h call pgm inc r3 jr nz, adr ld r8,#0ffh ; dummy data call pgm sb1 and fmcon,#01111111b ; sdat=0 and fmcon,#11111110b ; sclk=0, stop sb0 ld pp,#88h ld 00h,#00h ; user program mode disable ld pp,#00h s3c84bb/f84bb embedded flash memory interface 18-11 programming tip ? programming (continued) sb1 rel: and fmcon,#11111101b ; flag disable tm fmcon,#00000010b ; flag check jr nz, rel sb0 jp end_sym ; end pgm: sb1 and fmcon,#11111110b ; sclk=0 call wait ld r9, #08h ; rotate time pgmb: rl r8 ; msb -> lsb ldb fmcon.7,r8 ; fmcon.7 ? r8.0 or fmcon,#00000001b ; sclk=1 and fmcon,#11111110b ; sclk=0 djnz r9, pgmb or fmcon,#10000000b ; sdat=1 or fmcon,#00000001b ; sclk=1 sb0 ret wait: nop nop ld r15, #0ffh ; 00h <- ffh loop0: djnz r15, loop0 ret end_sym: nop .end embedded flash memory interface s3c84bb/f84bb 18-12 data protection option sector programming (protection option in user programming mode) user program mode can support hard lock protection and read protection when they have not been selected in tool program mode yet. the data programmed by a user flash memory need to be protected at the fields of application. the flash memory control block in the s3f84 bb protects the data with two protection modes: - hardware protection (hard lock protection) - read protection these protection modes can be enabled by the option sele ction at a tool program mode or setting the smart option at a user program mode. hardware protection (hard lock protection) if this function is enable user or any other thing cannot write and erase the data in a flash memory area. hard lock function can be set up in the tool program mode as well as a user program mode. besides this protection could be released (cleared) by the chip er ase execution at a tool program mode. read protection there are many users who do not want their code data to be read by any others. read protection solves this matter by preventing the flash data from being read serially at a tool program mode and is no effective at a user program mode. when this function is enable reading or verify ing the flash data at a tool program mode results in zero read out. read protection can be released (cleared) by the chip erase execution at a tool program mode. notes; 1. to enable hard lock protection, set the data of address 0e3eh to ?00h? in user program mode. 2. to enable read protection, set the data of addr ess 0e3fh to ?00h? in user program mode. s3c84bb/f84bb embedded flash memory interface 18-13 programming tip ? option sector programming (hard lock protection in user program mode) sb1 clr fmcon ; clear register sb0 ld clkcon, #00h ; cpu clock is 16-divide loope: nop ld pp, #88h ; ld 00h,#0a5h ; user program mode enable ld pp,#00h ; sb1 ent: or fmcon,#00000010b ; flag enable tm fmcon,#00000010b ; flag check jr z, ent sb0 spgm: sb1 ; start or fmcon,#00000001b ; sclk=1 or fmcon,#10000000b ; sdat=1 sb0 ld r8,#11100000b ; 1?st byte (hard lock protection mode) call pgm ld r8,#00001110b ; 2nd byte=0e3eh call pgm ld r8,#00111110b ; 3rd byte call pgm ld r8,#00h ; data = 00h(hard lock data) call pgm ld r8,#0ffh ; dummy data call pgm sb1 and fmcon,#01111111b ; sdat=0 and fmcon,#11111110b ; sclk=0, stop sb0 ld pp,#88h ld 00h,#00h ; user program mode disable ld pp,#00h embedded flash memory interface s3c84bb/f84bb 18-14 programming tip ? option sector progra mming (hard lock protection - continued) sb1 rel: and fmcon,#11111101b ; flag disable tm fmcon,#00000010b ; flag check jr nz, rel sb0 jp end_sym ; end pgm: sb1 and fmcon,#11111110b ; sclk=0 call wait ld r9, #08h ; rotate time pgmb: rl r8 ; msb -> lsb ldb fmcon.7,r8 ; fmcon.7 ? r8.0 or fmcon,#00000001b ; sclk=1 and fmcon,#11111110b ; sclk=0 djnz r9, pgmb or fmcon,#10000000b ; sdat=1 or fmcon,#00000001b ; sclk=1 sb0 ret wait: nop nop ld r15, #0ffh ; 00h <- ffh loop0: djnz r15, loop0 ret end_sym: nop .end note: it is possible to adopt protection option (read or har d lock protection) in user program mode only when it hasn?t been adopted by the programmer tools (in tool mode before). s3c84bb/f84bb electrical data 19-1 19 electrical data overview in this chapter, s3c84bb/f84bb electrical characteristics are presented in tables and graphs. the information is arranged in the following order: ? absolute maximum ratings ? input/output capacitance ? d.c. electrical characteristics ? a.c. electrical characteristics ? oscillation characteristics ? oscillation stabilization time ? data retention supply voltage in stop mode ? a/d converter electrical characteristics electrical data s3c84bb/f84bb 19-2 table 19-1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? 0.3 to +6.5 v input voltage v i ? 0.3 to v dd + 0.3 output voltage v o ? 0.3 to v dd + 0.3 output current high i oh one i/o pin active ? 18 ma all i/o pins active ? 60 output current low i ol one i/o pin active +30 total pin current for port +100 operating temperature t a ? 40 to + 85 storage temperature t stg ? 65 to + 150 c table 19-2. d.c. electrical characteristics (t a = -25 c to + 85 c, v dd = 2.7 v to 5.5 v) parameter symbol conditions min typ max unit operating voltage v dd f cpu = 10 mhz 2.7 ? 5.5 v input high voltage v ih1 all input pins except v ih2 0.8 v dd ? v dd v ih2 x in v dd -0.5 v dd input low voltage v il1 all input pins except v il2 ? ? 0.2 v dd v il2 x in ? 0.4 s3c84bb/f84bb electrical data 19-3 table 19-2. d.c. electrical characteristics (continued) (t a = -25 c to + 85 c, v dd = 2.7 v to 5.5 v) parameter symbol conditions min typ max unit output high voltage v oh1 v dd = 5 v; i oh = -1 ma all output pins except port 0,2,6 v dd ? 1.0 ? ? v v oh2 v dd = 5 v; i oh = -4 ma port 0,2 v dd ? 2.0 output low voltage v ol1 v dd = 5 v; i ol = 2 ma all output pins except port 0,2,6 ? 0.12 2.0 v ol2 v dd = 5 v; i ol = 15 ma port 0,2,6 0.6 2.0 input high leakage current i lih1 v in = v dd all input pins except i lih2 ? ? 3 a i lih2 v in = v dd x in 20 input low leakage current i lil1 v in = 0 v all input pins except i lil2 ? ? -3 i lil2 v in = 0 v x in -20 output high leakage current i loh v out = v dd all i/o pins and output pins ? ? 5 output low leakage current i lol v out = 0 v all i/o pins and output pins ? ? -5 pull-up resistor r l1 v in = 0 v; v dd = 5 v 10 % port 0?8, t a = 25 c 30 46 80 k ? r l2 v in = 0 v; v dd = 5 v 10% reset only, t a =25 c 120 240 320 electrical data s3c84bb/f84bb 19-4 table 19-2. d.c. electrical characteristics (concluded) (t a = -25 c to + 85 c, v dd = 2.7 v to 5.5 v) parameter symbol conditions min typ max unit supply current (1) i dd1 v dd = 5 v 10 % 10 mhz crystal oscillator ? 8.5 20 ma i dd2 idle mode: v dd = 5 v 10 % 10 mhz crystal oscillator 2.5 5 i dd3 stop mode: v dd = 5 v 10 % t a = 25 c 1 3 a notes: 1. supply current does not include current drawn through internal pull-up resistor s or external output current loads. s3c84bb/f84bb electrical data 19-5 table 19-3. a.c. electrical characteristics (t a = -25 c to +85 c, v dd = 2.7 v to 5.5 v) parameter symbol conditions min typ max unit interrupt input high, low width (p4.0?p4.7) (p8.5, p8.6) t inth , t intl v dd = 5 v 180 ? ? ns reset input low width t rsl v dd = 5 v 1.0 ? ? s note: user must keep more large value then min value. t intl 0.8 v dd 0.2 v dd t inth 0.2 v dd figure 19-1. input timing for external inte rrupts (ports 4, port 8.5, port 8.6) reset t rsl 0.2 v dd figure 19-2. input timing for reset electrical data s3c84bb/f84bb 19-6 table 19-4. input/output capacitance (t a = -25 c to +85 c, v dd = 0 v ) parameter symbol conditions min typ max unit input capacitance c in f = 1 mhz; unmeasured pins are tied to v ss ? ? 10 pf output capacitance c out i/o capacitance c io table 19-5. data retention supply voltage in stop mode (t a = -25 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr stop mode 2 ? 5.5 v data retention supply current i dddr v dddr = 2.0 v, stop mode ? ? 3 a execution of stop instrction reset occurs ~ ~ v dddr ~ ~ stop mode oscillation stabilization time normal operating mode data retention mode t wait reset v dd note: t wait is the same as 4096 x 16 x 1/f osc 0.2 v dd figure 19-3. stop mode release timing initiated by reset s3c84bb/f84bb electrical data 19-7 execution of stop instruction ~ ~ v dddr ~ ~ stop mode idle mode data retention mode t wait v dd interrupt normal operating mode oscillation stabilization time 0.2 v dd note: t wait is the same as 4096 x 16 x bt clock figure 19-4. stop mode release timing initiated by interrupts electrical data s3c84bb/f84bb 19-8 table 19-6. a/d converter electrical characteristics (t a = - 25 c to +85 c, v dd = 2.7 v to 5.5 v, v ss = 0 v) parameter symbol conditions min typ max unit resolution ? 10 ? bit total accuracy v dd = 5.12 v ? ? 3 integral linearity error ile av ref = 5.12v ? ? 2 differential linearity error dle av ss = 0 v fxx = 10 mhz ? ? 1 offset error of top eot ? 1 3 offset error of bottom eob ? 0.5 2 lsb conversion time (1) t con 10-bit resolution 50 x 4/fxx, fxx = 10mhz 20 ? ? s analog input voltage v ian ? av ss ? av ref v analog input impedance r an ? 2 1000 ? m ? analog reference voltage av ref ? 2.5 ? v dd v analog ground av ss ? v ss ? v ss +0.3 analog input current i adin av ref = v dd = 5v ? ? 10 a analog block current (2) i adc av ref = v dd = 5v ? 1 3 av ref = v dd = 3v 0.5 1.5 ma av ref = v dd = 5v when power down mode 100 500 na notes: 1. 'conversion time' is the time required from t he moment a conversion operat ion starts until it ends. 2. i adc is an operating current during a/d conversion. table 19-7. d/a converter electrical characteristics (t a = - 25 c to +85 c, v dd = 2.7 v to 5.5 v, v ss = 0 v) parameter symbol conditions min typ max unit resolution ? ? ? ? 8 bits absolute accuracy ? ? 3 ? 3 lsb differential linearity error dle ? 1 ? 1 lsb setup time t su ? ? 5 s output resistance r o 4.5 5 5.5 k ? s3c84bb/f84bb electrical data 19-9 table 19-8. flash memory d.c. electrical characteristics (t a = - 25 c to +85 c, v dd = 2.7 v to 5.5 v, v ss = 0 v) parameter symbol conditions min typ max unit logic power supply v dd 2.7 5.0 5.5 v f dd1 v dd = 2.7 v to 5.5 v during reading ? 40 80 ma f dd2 v dd = 2.7 v to 5.5 v during programming ? 40 80 ma flash memory operating current (f dd ) f dd3 v dd = 2.7 v to 5.5 v during erasing ? 40 80 ma table 19-9. flash memory a.c. electrical characteristics (t a = - 25 c to +85 c, v dd = 2.7 v to 5.5 v, v ss = 0 v) parameter symbol conditions min typ max unit programming time (1) ftp 20 30 300 us chip erasing time (2) ftp1 ? ? 10 ms sector erasing time (3) ftp2 ? 2 ms data access time ft rs v dd = 2.7 v to 5.5 v ? 50 ? ms number of writing/erasing fnwe ? ? 100 times notes: 1. the programming time is the time dur ing which one byte(8-bit) is programmed. 2. the chip erasing time is the time during which all 64k-byte block is erased. 3. the sector erasing time is the time during which all 60k-byte block is erased. electrical data s3c84bb/f84bb 19-10 table 19-10. main oscillator frequency (f osc1 ) (t a = -25 c to +85 c, v dd = 2.7 v to 5.5 v) oscillator clock circuit test condition min typ max unit crystal x in c1 c2 x out crystal oscillation frequency 1 ? 10 mhz ceramic x in c1 c2 x out ceramic oscillation frequency 1 ? 10 external clock x in x out x in input frequency 1 ? 10 table 19-11. main oscillator clock stabilization time (t st1 ) (t a = -25 c to +85 c, v dd = 2.7 v to 5.5 v) oscillator test condition min typ max unit crystal ? ? 10 ms ceramic v dd = 2.7 v to 5.5 v stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 4 external clock x in input high and low level width (t xh , t xl ) 50 ? ? ns note: oscillation stabilization time (t st1 ) is the time required for the cpu clo ck to return to its normal oscillation frequency after a power-on occurs, or when stop mode is ended by a reset signal. s3c84bb/f84bb electrical data 19-11 x in t xh t xl 1/f osc1 v dd - 0.5 v 0.4 v figure 19-5. clock timing measurement at x in 12 mhz 4 mhz 1 mhz 567 supply voltage (v) minimum instruction clock = 1/4 x oscillator frequency 5.5 10 mhz 3.3 a b 4 3 2.7 1 f cpu mask type/ flash type figure 19-6. operating voltage range electrical data s3c84bb/f84bb 19-12 notes s3c84bb/f84bb mechanical data 20?1 mechanical data note : dimensions are in millimeters. 17.90 ?0.3 14.00 ?0.2 (1.00) 80-qfp-1420c 23.90 ?0.3 #80 (0.80) #1 0.35 ?0.1 0.15 max 0.80 ?0.20 0.10 max 0.15 +0.10 - 0.05 0~8 2.65 ?0.10 3.00 max 0.05 min 0.80 ?0.20 20.00 ?0.2 0.80 figure 20?1. s3c84bb/f84bb 80-qfp standard package dimension (in millimeters) mechanical data s3c84bb/f84bb 20?2 not e : dimensions are in millimeters. 14.0 0bsc 12.00bsc 80-tqfp-1212-an 14.00bsc 12.00bsc #80 (1.25) #1 0.50 0.17~0.27 0.65 0.15 0.10 max 0.09~0.20 0~7 1.00 0 .05 1.20 max 0.05~0.15 0.25gauge plane 0.08 max m figure 20?2. s3c84bb/f84bb 80-tqfp standard package dimension (in millimeters) s3c84bb/f84bb development tools 21-1 development tools overview samsung provides a powerful and easy-to-use development support system in turnkey form. the development support system is configured with a host system, debugging tools, and support software. for the host system, any standard computer that operates with win95/98/2000 as its operating system can be used. one type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, smds2+ or sk-1000, for s3c7, s3c9, s3c8 families of microcontrollers. the smds2+ and sk-1000 is a new and improved version of smds2. samsung also offers support software that includes debugger, assembler, and a program for setting options. shine samsung host interface for in-circuit emulator, shine (smart studio in case of sk-1000), is a multi-window based debugger for smds2+. shine provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. it has an advanced, multiple-windowed user interface that emphasizes ease of use. each window can be sized, moved, scrolled, highlighted, added, or removed completely. sasm assembler the sasm88 is a relocatable assembler for samsung's s3c8-series microcontrollers. the sasm88 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. the sasm88 supports macros and conditional assembly. it runs on the ms-dos operating system. it produces the relocatable object code only, so the user should link object file. object files can be linked with other object files and loaded into memory. sama assembler the samsung arrangeable microcontroller (sam) assembler, sama, is a universal assembler, and generates object code in standard hexadecimal format. assembled program code includes the object code that is used for rom data and required smds program control data. to assemble programs, sama requires a source file and an auxiliary definition (def) file with device specific information. hex2rom hex2rom file generates rom code from hex file which has been produced by assembler. rom code must be needed to fabricate a microcontroller which has a mask rom. when generating the rom code (.obj file) by hex2rom, the value "ff" is filled into the unused rom area up to the maximum rom size of the target device automatically. target boards target boards are available for all s3c8-series microcontrollers. all required target system cables and adapters are included with the device-specific target board. development tools s3c84bb/f84bb 21-2 smds2+ rs-232c pod probe adapter tb84bb target board ibm-pc at or compatible prom/otp writer unit bus ram break/display unit trace/timer unit sam8 base unit power supply unit target application system eva chip figure 21-1. smds+ product configuration (sk-1000 is single cabinet type) s3c84bb/f84bb development tools 21-3 tb84bb target board the tb84bb target board is used for the s3c84bb/f84bb microcontroller. it is supported by the smds2, smds2+, sk-820, or sk-1000 development system. tb84bb sm1xxxa reset1 to user_v cc off on 40-pin connector 2 1 39 40 25 1 j101 160 qfp s3e84bb eva chip gnd v cc cn1 + stop + idle 40-pin connector 2 1 39 40 j102 external triggers ch1 ch2 figure 21?2. tb84bb target board configuration development tools s3c84bb/f84bb 21-4 table 21-1. power selection settings for tb84bb "to user_v cc " settings operating mode comments to user_v cc off on target system sk-1000/smds2+ tb84bb v cc v ss v cc the ice (sk-1000/smds2+ ) supplies v cc to the target board (evaluation chip) and the target system. to user_v cc off on tb84bb target system sk-1000/smds2+ external v cc v ss v cc the ice (sk-1000/smds2+) supplies v cc only to the target board (evaluation chip). the target system must have its own power supply. s3c84bb/f84bb development tools 21-5 table 21-2. using single header pins as the input path for external trigger sources target board part comments external triggers ch1 ch2 connector from external trigger sources of the application system you can connect an external trigger source to one of the two external trigger channels (ch1 or ch2) only for the smds2+ breakpoint and trace functions. idle led the green led is on when the evaluation chip (s3e84bb) is in idle mode. stop led the red led is on when the evaluation chip (s3e84bb) is in stop mode. development tools s3c84bb/f84bb 21-6 p7.5/adc5 avref p7.3/adc3 p7.1/adc1 p6.7 p6.5 vdd2 p6.3 p6.1 p8.5/int9 p8.3 p8.1 p1.7 p1.5 p1.3 p1.1 p0.7/pg7 p0.5/pg5 p0.3/pg3 p0.1/pg1 p7.4/adc4 avss p7.2/adc2 p7.0/adc0 p6.6 vss2 p6.4 p6.2 p6.0 p8.4/int8 p8.2 p8.0 p1.6 p1.4 p1.2 p1.0 p0.6/pg6 p0.4/pg4 p0.2/pg2 p0.0/pg0 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 p2.7/taout p2.5/tack p2.3/daout p2.1/si p5.7 p5.5 vss1 n.c p5.4 resetb p5.1/rxd1 p3.7/tcout1 p3.5/t1out1 p3.3/t1cap1 p3.1/t1ck1 p4.7/int7 p4.5/int5 p4.3/int3 p4.1/int1 p7.7/adc7 p2.6/tacap p2.4/tbpwm p2.2/sck p2.0/so p5.6 vdd1 n.c n.c(test) p5.3/rxd0 p5.2/txd0 p5.0/txd1 p3.6/tcout0 p3.4/t1out0 p3.2/t1cap0 p3.0/t1ck0 p4.6/int6 p4.4/int4 p4.2/int2 p4.0/int0 p7.6/adc6 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 figure 21?3. 40-pin connectors for tb84bb (s3c84bb, 80-qfp package) !"# $ # % " &'' figure 21?4. tb84bb cable for 80-qfp adapter (for duplicate copies of this form, and for additional ordering information, please contact your local samsung sales representative. samsung sales offices are listed on the back cover of this book.) s3c series mask rom order form product description: device number: s3c84bb______- ___________(write down the rom code number) product order form: package pellet wafer package type: __________ package marking (check one): standard custom a custom b (max 10 chars) (max 10 chars each line) @ : assembly site code, y : last number of assembly year, ww : week of assembly @ yww device name sec device name @ yww @ yww delivery dates and quantities: deliverable required delivery date quantity comments rom code ? not applicable see rom selection form customer sample risk order see risk order sheet please answer the following questions: for what kind of product will you be using this order? new product upgrade of an existing product replacement of an existing product other if you are replacing an existing product, please indicate the former product name ( ) what are the main reasons you decided to use a samsung microcontroller in your product? please check all that apply. price product quality features and functions development system technical support delivery on time used same micom before quality of documentation samsung reputation mask charge (us$ / won): ____________________________ customer information: company name: ___________________ telephone number _________________________ signatures: ________________________ __________________________________ (person placing the order) (technical manager) (for duplicate copies of this form, and for additional ordering information, please contact your local samsung sales representative. samsung sales offices are listed on the back cover of this book.) s3c series request for production at customer risk customer information: company name: ________________________________________________________________ department: ________________________________________________________________ telephone number: __________________________ fax: _____________________________ date: __________________________ risk order information: device number: s3c________- ________ (write down the rom code number) package: number of pins: ____________ package type: _____________________ intended application: ________________________________________________________________ product model number: ________________________________________________________________ customer risk order agreement: we hereby request sec to produce the above named product in the quantity stated below. we believe our risk order product to be in full compliance with all sec production specifications and, to this extent, agree to assume responsibility for any and all production risks involved. order quantity and delivery schedule: risk order quantity: _____________________ pcs delivery schedule: delivery date (s) quantity comments signatures: _______________________________ _______________________________________ (person placing the risk order) (sec sales representative) (for duplicate copies of this form, and for additional ordering information, please contact your local samsung sales representative. samsung sales offices are listed on the back cover of this book.) s3c84bb mask option selection form device number: s3c___-________(write down the rom code number) attachment (check one): diskette prom customer checksum: ________________________________________________________________ company name: ________________________________________________________________ signature (engineer): ________________________________________________________________ please answer the following questions: application (product model id: _______________________) audio video telecom cd databank caller id cd game industrials home appliance office automation remocon other please describe in detail its application (for duplicate copies of this form, and for additional ordering information, please contact your local samsung sales representative. samsung sales offices are listed on the back cover of this book.) s3f84bb series flash mcu factory writing order form (1/2) product description: device number: s3f84bb__-________(write down the rom code number) product order form: package pellet wafer if the product order form is package: package type: _____________________ package marking (check one): standard custom a custom b (max 10 chars) (max 10 chars each line) @ : assembly site code, y : last number of assembly year, ww : week of assembly @ yww device name sec device name @ yww @ yww delivery dates and quantity: rom code release date required delivery date of device quantity please answer the following questions: what is the purpose of this order? new product development upgrade of an existing product replacement of an existing microcontroller other if you are replacing an existing microcontroller, please indicate the former microcontroller name ( ) what are the main reasons you decided to use a samsung microcontroller in your product? please check all that apply. price product quality features and functions development system technical support delivery on time used same mcu before quality of documentation samsung reputation customer information: company name: ___________________ telephone number _________________________ signatures: ________________________ __________________________________ (person placing the order) (technical manager) (for duplicate copies of this form, and for additional ordering information, please contact your local samsung sales representative. samsung sales offices are listed on the back cover of this book.) s3f84bb flash mcu factory writing order form (2/2) device number: s3f84bb__-__________ (write down the rom code number) customer checksums: _______________________________________________________________ company name: ________________________________________________________________ signature (engineer): ________________________________________________________________ read protection (1) : yes no please answer the following questions: are you going to continue ordering this device? yes no if so, how much will you be ordering? _________________pcs application (product model id: _______________________) audio video telecom lcd databank caller id lcd game industrials home appliance office automation remocon other please describe in detail its application ___________________________________________________________________________ notes 1. once you choose a read protection, you cannot read again the programming code from the rom. 2. flash mcu writing will be executed in our manufacturing site. 3. the writing program is completely verified by a customer. samsung does not take on any responsibility for errors occurred from the writing program. |
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